diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2020-06-11 14:08:17 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-14 16:53:31 +0000 |
| commit | c64755bcd70031620e606d30fd095ef6362b5975 (patch) | |
| tree | 66f4e701f26b8f0ded943f5442be032da15e6e36 /src | |
| parent | d53c281d0beeabcfafd4b2682fbd0c01ae88ac10 (diff) | |
soc/amd/picasso/aoac: Set the Target Device State when powering on
If the OS sets the target device state to D3, we need to clear it so we
can reestablish register access.
BUG=b:153001807
TEST=Boot trembyle with I2C powered off and see it power back on.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/picasso/aoac.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 35adc24723..2e00d98900 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -36,6 +36,8 @@ void power_on_aoac_device(int dev) /* Power on the UART and AMBA devices */ byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; + byte &= ~FCH_AOAC_TARGET_DEVICE_STATE; + byte |= FCH_AOAC_D0_INITIALIZED; aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 463ca296aa..7265d30a77 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -207,6 +207,10 @@ /* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) +#define FCH_AOAC_D0_UNINITIALIZED 0 +#define FCH_AOAC_D0_INITIALIZED 1 +#define FCH_AOAC_D1_2_3_WARM 2 +#define FCH_AOAC_D3_COLD 3 #define FCH_AOAC_DEVICE_STATE BIT(2) #define FCH_AOAC_PWR_ON_DEV BIT(3) #define FCH_AOAC_SW_PWR_ON_RSTB BIT(4) |