fix digitallogic adl855pc compilation (and clean up the warnings while at it)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 10 insertions, 93 deletions

diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c
index 2e1a96c91b..731e681253 100644
--- a/src/mainboard/digitallogic/adl855pc/romstage.c
+++ b/src/mainboard/digitallogic/adl855pc/romstage.c
@@ -3,12 +3,10 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#if 0
-#include <arch/smp/lapic.h>
-#endif
 #include <arch/hlt.h>
 //#include "option_table.h"
 #include <stdlib.h>
+#include "pc80/udelay_io.c"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "console/console.c"
@@ -16,13 +14,6 @@
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
 #include "northbridge/intel/i855/raminit.h"
-
-#if 0
-#include "cpu/p6/apic_timer.c"
-#include "lib/delay.c"
-#endif
-
-#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/i855/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c" 
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -30,24 +21,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
-{
-        outb(0x0e, 0x0cf9);
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -57,10 +30,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/i855/reset_test.c"
 #include "lib/generic_sdram.c"
 
-
-#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
-
-void real_main(unsigned long bist)
+void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {
 		{
@@ -93,7 +63,6 @@ void real_main(unsigned long bist)
 		dump_spd_registers(&memctrl[0]);
 		dump_smbus_registers();
 #endif
-		memreset_setup();
 
 		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 40da896589..c353776c12 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -18,24 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/*
- * generic K8 debug code, used by mainboard specific romstage.c
- *
- */
-#if 1
-/*
-static void print_debug_pci_dev(unsigned dev)
-{
-	print_debug("PCI: ");
-	print_debug_hex8((dev >> 16) & 0xff);
-	print_debug_char(':');
-	print_debug_hex8((dev >> 11) & 0x1f);
-	print_debug_char('.');
-	print_debug_hex8((dev >> 8) & 7);
-}
-*/
-
-
 static void print_debug_pci_dev(unsigned dev)
 {
 	print_debug("PCI: ");
@@ -46,7 +28,7 @@ static void print_debug_pci_dev(unsigned dev)
 	print_debug_hex8((dev >> 12) & 0x07);
 }
 
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
 {
 	device_t dev;
 	for(dev = PCI_DEV(0, 0, 0); 
@@ -85,7 +67,7 @@ static void dump_pci_device(unsigned dev)
 	}
 }
 
-static void dump_pci_devices(void)
+static inline void dump_pci_devices(void)
 {
 	device_t dev;
 	for(dev = PCI_DEV(0, 0, 0); 
@@ -102,7 +84,7 @@ static void dump_pci_devices(void)
 	}
 }
 
-static void dump_spd_registers(const struct mem_controller *ctrl)
+static inline void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
 	print_debug("\n");
@@ -134,37 +116,10 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
 			}
 			print_debug("\n");
 		}
-#if 0
-		device = ctrl->channel1[i];
-		if (device) {
-			int j;
-			print_debug("dimm: "); 
-			print_debug_hex8(i); 
-			print_debug(".1: ");
-			print_debug_hex8(device);
-			for(j = 0; j < 256; j++) {
-				int status;
-				unsigned char byte;
-				if ((j & 0xf) == 0) {
-					print_debug("\n");
-					print_debug_hex8(j);
-					print_debug(": ");
-				}
-				status = smbus_read_byte(device, j);
-				if (status < 0) {
-					print_debug("bad device\n");
-					break;
-				}
-				byte = status & 0xff;
-				print_debug_hex8(byte);
-				print_debug_char(' ');
-			}
-			print_debug("\n");
-		}
-#endif
 	}
 }
-static void dump_smbus_registers(void)
+
+static inline void dump_smbus_registers(void)
 {
         int i;
         print_debug("\n");
@@ -194,4 +149,3 @@ static void dump_smbus_registers(void)
                 print_debug("\n");
 	}	
 }
-#endif
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 136266da2c..5d71a27ca1 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -19,6 +19,7 @@
  */
  
 #include <sdram_mode.h>
+#include <delay.h>
 
 #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))
 #define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5)
@@ -85,20 +86,11 @@ static void spd_set_dram_throttle_control(const struct mem_controller *ctrl)
 	pci_write_config32(ctrl->d0, 0xa0, dtc_reg);
 }
 
-void udelay(int usecs)
-{
-        int i;
-        for(i = 0; i < usecs; i++)
-                outb(i & 0xff, 0x80);
-}
-
 #define delay() udelay(200)
 
 /* if ram still doesn't work do this function */
 static void spd_set_undocumented_registers(const struct mem_controller *ctrl)
 {
-	uint16_t word;
-	
 	/* 0:0.0 */
 	/*
 	pci_write_config32(PCI_DEV(0, 0, 0), 0x10, 0xe0000008);
diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h
index a312ee511f..dbd0be6927 100644
--- a/src/northbridge/intel/i855/raminit.h
+++ b/src/northbridge/intel/i855/raminit.h
@@ -28,5 +28,7 @@ struct mem_controller {
   uint16_t channel0[DIMM_SOCKETS];
 };
 
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+
 
 #endif /* RAMINIT_H */