mb/msi/ms7e06: Add support for MSI PRO Z790-P DDR4/DDR5 (WIFI)

TEST=Boot Ubuntu 22.04 on MSI PRO Z790-P (DDR5 variant) with Intel Core
i5-13600K using UEFI Payload.

Change-Id: Id2c77621d24bb097b930342eb1961270854d5f68
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76325
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

16 files changed, 2022 insertions, 0 deletions

diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig
new file mode 100644
index 0000000000..8dca3fc3b6
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/Kconfig
@@ -0,0 +1,74 @@
+config BOARD_MSI_Z790_P_PRO_WIFI_DDR4
+	select BOARD_MSI_MS7E06
+
+config BOARD_MSI_Z790_P_PRO_WIFI
+	select BOARD_MSI_MS7E06
+
+config BOARD_MSI_MS7E06
+	def_bool n
+	select SOC_INTEL_RAPTORLAKE_PCH_S
+	select FSP_TYPE_IOT
+	select BOARD_ROMSIZE_KB_32768
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SUPERIO_NUVOTON_NCT6687D
+	select DRIVERS_UART_8250IO
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_GMA_HAVE_VBT
+	select CRB_TPM
+	select HAVE_INTEL_PTT
+
+if BOARD_MSI_MS7E06
+
+config MAINBOARD_DIR
+	default "msi/ms7e06"
+
+config MAINBOARD_PART_NUMBER
+	default "PRO Z790-P WIFI DDR4(MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI_DDR4
+	default "PRO Z790-P WIFI (MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI
+
+config MAINBOARD_VENDOR
+	default "Micro-Star International Co., Ltd."
+
+config MAINBOARD_FAMILY
+	default "Default string"
+
+config DIMM_SPD_SIZE
+	default 512
+
+config UART_FOR_CONSOLE
+	default 0
+
+config USE_PM_ACPI_TIMER
+	default n
+
+config USE_LEGACY_8254_TIMER
+	default y
+
+config CBFS_SIZE
+	default 0x1000000
+
+config VBOOT
+	select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+	select GBB_FLAG_DISABLE_FWMP
+	select GBB_FLAG_DISABLE_LID_SHUTDOWN
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select VBOOT_ALWAYS_ENABLE_DISPLAY
+	select VBOOT_NO_BOARD_SUPPORT
+	select HAS_RECOVERY_MRC_CACHE
+
+config VBOOT_SLOTS_RW_AB
+	default y if VBOOT
+
+config SOC_INTEL_CSE_SEND_EOP_EARLY
+	default n
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB
+
+# gen_test_hwid.sh script doesn't like parentheses in the MAINBOARD_PART_NUMBER
+# Override the GBB_HWID
+config GBB_HWID
+	default "MSI_MS7E06"
+
+endif
diff --git a/src/mainboard/msi/ms7e06/Kconfig.name b/src/mainboard/msi/ms7e06/Kconfig.name
new file mode 100644
index 0000000000..c386ffd7c4
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/Kconfig.name
@@ -0,0 +1,5 @@
+config BOARD_MSI_Z790_P_PRO_WIFI_DDR4
+	bool "PRO Z790-P (WIFI) DDR4"
+
+config BOARD_MSI_Z790_P_PRO_WIFI
+	bool "PRO Z790-P (WIFI)"
diff --git a/src/mainboard/msi/ms7e06/Makefile.inc b/src/mainboard/msi/ms7e06/Makefile.inc
new file mode 100644
index 0000000000..deb5ff625a
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/Makefile.inc
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += romstage_fsp_params.c
+
+ramstage-y += mainboard.c
+
+all-y += die.c
+smm-y += die.c
diff --git a/src/mainboard/msi/ms7e06/acpi/mainboard.asl b/src/mainboard/msi/ms7e06/acpi/mainboard.asl
new file mode 100644
index 0000000000..8cc72ab68d
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/acpi/mainboard.asl
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+Scope (_GPE) {
+	/* Empty PCI_EXP_STS handler */
+	Method (_L69, 0, Serialized) { }
+}
+
+Scope (\_SB.PCI0) {
+	/* This device triggers automatic drivers and MSI utilities installation on Windows */
+	Device (MSIV) {
+		Name (_HID, "MBID0001")
+		Name (_UID, 1)
+		Method (_STA, 0, NotSerialized){
+			Return (1)
+		}
+	}
+}
diff --git a/src/mainboard/msi/ms7e06/acpi/superio.asl b/src/mainboard/msi/ms7e06/acpi/superio.asl
new file mode 100644
index 0000000000..35c6bce088
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/acpi/superio.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x4e
+#define NCT6687D_SHOW_SP1
+#define NCT6687D_SHOW_KBC
+#define NCT6687D_SHOW_EC
+
+#include <superio/nuvoton/nct6687d/acpi/superio.asl>
diff --git a/src/mainboard/msi/ms7e06/board_info.txt b/src/mainboard/msi/ms7e06/board_info.txt
new file mode 100644
index 0000000000..5fe171e09e
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.msi.com/Motherboard/PRO-Z790-P-WIFI-DDR4
+ROM IC: MX25U25673G
+ROM package: WSON-8
+ROM socketed: no
+Flashrom support: yes
+Release year: 2022
diff --git a/src/mainboard/msi/ms7e06/bootblock.c b/src/mainboard/msi/ms7e06/bootblock.c
new file mode 100644
index 0000000000..110d6828a6
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/bootblock.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6687d/nct6687d.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1)
+#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Replicate vendor settings for multi-function pins in global config LDN */
+	nuvoton_pnp_enter_conf_state(SERIAL_DEV);
+	pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low
+	pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low
+
+	/* Below are multi-pin function */
+	pnp_write_config(SERIAL_DEV, 0x15, 0xaa);
+	pnp_write_config(SERIAL_DEV, 0x1a, 0x02);
+	pnp_write_config(SERIAL_DEV, 0x1b, 0x02);
+	pnp_write_config(SERIAL_DEV, 0x1d, 0x00);
+	pnp_write_config(SERIAL_DEV, 0x1e, 0xaa);
+	pnp_write_config(SERIAL_DEV, 0x1f, 0xb2);
+	pnp_write_config(SERIAL_DEV, 0x22, 0xbd);
+	pnp_write_config(SERIAL_DEV, 0x23, 0xdf);
+	pnp_write_config(SERIAL_DEV, 0x24, 0x39);
+	pnp_write_config(SERIAL_DEV, 0x25, 0xfe);
+	pnp_write_config(SERIAL_DEV, 0x26, 0x40);
+	pnp_write_config(SERIAL_DEV, 0x27, 0x77);
+	pnp_write_config(SERIAL_DEV, 0x28, 0x00);
+	pnp_write_config(SERIAL_DEV, 0x29, 0xfb);
+	pnp_write_config(SERIAL_DEV, 0x2a, 0x80);
+	pnp_write_config(SERIAL_DEV, 0x2b, 0x20);
+	pnp_write_config(SERIAL_DEV, 0x2c, 0x8a);
+	pnp_write_config(SERIAL_DEV, 0x2d, 0xaa);
+
+	pnp_set_logical_device(POWER_DEV);
+	/* Configure pin for PECI */
+	pnp_write_config(POWER_DEV, 0xf3, 0x80);
+
+	nuvoton_pnp_exit_conf_state(POWER_DEV);
+
+	if (CONFIG(CONSOLE_SERIAL))
+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/msi/ms7e06/data.vbt b/src/mainboard/msi/ms7e06/data.vbt
new file mode 100644
index 0000000000..31a309cb3c
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/data.vbt
diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb
new file mode 100644
index 0000000000..65ba314feb
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/devicetree.cb
@@ -0,0 +1,247 @@
+chip soc/intel/alderlake
+	# FSP configuration
+
+	register "eist_enable" = "1"
+
+	# Sagv Configuration
+	register "sagv" = "SaGv_Enabled"
+	register "RMT" = "0"
+	register "enable_c6dram" = "1"
+
+	register "pmc_gpe0_dw0" = "GPP_J"
+	register "pmc_gpe0_dw1" = "GPP_VPGIO"
+	register "pmc_gpe0_dw2" = "GPD"
+
+	register "hybrid_storage_mode" = "1"
+	register "dmi_power_optimize_disable" = "1"
+
+	# FIVR configuration
+	register "fivr_rfi_frequency" = "1394"
+	register "fivr_spread_spectrum" = "FIVR_SS_1_5"
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+	}"
+
+	device domain 0 on
+		subsystemid 0x1462 0x7e06 inherit
+		device ref pcie5_0 on
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong"
+					 "PCI_E1" "SlotDataBusWidth16X"
+		end
+		device ref igpu on
+			# HDMI on port B
+			register "ddi_portB_config" = "1"
+			register "ddi_ports_config" = "{
+				[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_2] = DDI_ENABLE_HPD,
+				[DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+				[DDI_PORT_4] = DDI_ENABLE_HPD,
+			}"
+		end
+		device ref pcie4_0 on
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 9,
+				.clk_req = 9,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M2_1" "SlotDataBusWidth4X"
+		end
+		device ref xhci on
+			register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1
+			register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT
+			register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1
+			register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5
+			register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0
+			register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty?
+			register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4
+			register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4
+			register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3
+			register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3
+			register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1
+			register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1
+			register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers
+			register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT
+			register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1
+			register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2
+
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2
+			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2
+			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4
+			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4
+			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3
+			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3
+			register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+		end
+		device ref cnvi_wifi on
+			# Enable CNVi BT
+			register "cnvi_bt_core" = "true"
+			register "cnvi_bt_audio_offload" = "false"
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				register "enable_cnvi_ddr_rfim" = "true"
+				device generic 0 on end
+			end
+		end
+		device ref heci1 on end
+		device ref sata on
+			register "sata_salp_support" = "1"
+
+			register "sata_ports_enable" = "{
+				[0] = 1,
+				[1] = 1,
+				[2] = 1,
+				[3] = 1,
+				[4] = 1,
+				[5] = 1,
+				[6] = 1,
+				[7] = 1,
+			}"
+
+			register "sata_ports_dev_slp" = "{
+				[0] = 0,
+				[1] = 0,
+				[2] = 0,
+				[3] = 0,
+				[4] = 0,
+				[5] = 0,
+				[6] = 1,
+				[7] = 1,
+			}"
+		end
+		device ref pcie_rp1 on
+			register "pch_pcie_rp[PCH_RP(1)]" = "{
+				.clk_src = 10,
+				.clk_req = 10,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort"
+					 "PCI_E2" "SlotDataBusWidth1X"
+		end
+		device ref pcie_rp2 on
+			register "pch_pcie_rp[PCH_RP(2)]" = "{
+				.clk_src = 17,
+				.clk_req = 17,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
+					 "PCI_E4" "SlotDataBusWidth1X"
+		end
+		device ref pcie_rp3 on
+			# i225 Ethernet, Clock PM unsupported, onboard device
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 12,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
+			}"
+		end
+
+		device ref pcie_rp5 on
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 15,
+				.clk_req = 15,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypePciExpressGen4x16" "SlotLengthLong"
+					 "PCI_E3" "SlotDataBusWidth4X"
+		end
+
+		device ref pcie_rp9 on
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 13,
+				.clk_req = 13,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M2_3" "SlotDataBusWidth4X"
+		end
+
+		# These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports.
+		# There is an ASMedia switch on-board to mux the SATA ports 7, 8 and PCIe
+		# 9-12, 21-24 to M2_3 and M2_4 slots
+		device ref pcie_rp13 off end
+		device ref pcie_rp14 off end
+		device ref pcie_rp15 off end
+		device ref pcie_rp16 off end
+		device ref pcie_rp17 off end
+		device ref pcie_rp18 off end
+		device ref pcie_rp19 off end
+		device ref pcie_rp20 off end
+
+		device ref pcie_rp21 on
+			register "pch_pcie_rp[PCH_RP(21)]" = "{
+				.clk_src = 14,
+				.clk_req = 14,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M2_4" "SlotDataBusWidth4X"
+		end
+
+		device ref pcie_rp25 on
+			register "pch_pcie_rp[PCH_RP(25)]" = "{
+				.clk_src = 8,
+				.clk_req = 8,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
+					 "M2_2" "SlotDataBusWidth4X"
+		end
+		device ref pch_espi on
+			register "gen1_dec" = "0x00fc0201"
+			register "gen2_dec" = "0x003c0a01"
+			register "gen3_dec" = "0x000c03f1"
+			register "gen4_dec" = "0x000c0081"
+
+			chip superio/nuvoton/nct6687d
+				device pnp 4e.1 off end		# Parallel port
+				device pnp 4e.2 on		# COM1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				end
+				device pnp 4e.3 off end		# COM2, IR
+				device pnp 4e.5 on		# Keyboard
+					io 0x60 = 0x60
+					io 0x62 = 0x64
+					irq 0x70 = 1
+					irq 0x72 = 12
+				end
+				device pnp 4e.6 off end		# CIR
+				device pnp 4e.7 off end		# GPIO0-7
+				device pnp 4e.8 off end		# P80 UART
+				device pnp 4e.9 off end		# GPIO8-9, GPIO1-8 AF
+				device pnp 4e.a on		# ACPI
+					# Vendor firmware did not assign I/O and IRQ
+				end
+				device pnp 4e.b on		# EC
+					io 0x60 = 0xa20
+					# Vendor firmware did not assign IRQ
+				end
+				device pnp 4e.c off end		# RTC
+				device pnp 4e.d off end		# Deep Sleep
+				device pnp 4e.e off end		# TACH/PWM assignment
+				device pnp 4e.f off end		# Function register
+			end
+		end
+		device ref hda on
+			subsystemid 0x1462 0x9e06
+			register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+			register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+			register "pch_hda_idisp_codec_enable" = "true"
+		end
+		device ref smbus on end
+
+		chip drivers/crb
+			device mmio 0xfed40000 on end
+		end
+	end
+end
diff --git a/src/mainboard/msi/ms7e06/die.c b/src/mainboard/msi/ms7e06/die.c
new file mode 100644
index 0000000000..52b3338799
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/die.c
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <pc80/i8254.h>
+#include <soc/gpio.h>
+#include <delay.h>
+#include <gpio.h>
+
+static void beep_and_blink(void)
+{
+	static uint8_t blink = 0;
+	static uint8_t beep_count = 0;
+
+	gpio_set(GPP_E8, blink);
+	/* Beep 12 times at most, constant beeps may be annoying */
+	if (beep_count < 12) {
+		beep(800, 300);
+		mdelay(200);
+		beep_count++;
+	} else {
+		mdelay(500);
+	}
+
+	blink ^= 1;
+}
+
+void die_notify(void)
+{
+	if (ENV_POSTCAR)
+		return;
+
+	/* Make SATA LED blink and use PC SPKR */
+	gpio_output(GPP_E8, 0);
+
+	while (1) {
+		beep_and_blink();
+		beep_and_blink();
+		beep_and_blink();
+		beep_and_blink();
+		delay(2);
+	}
+}
diff --git a/src/mainboard/msi/ms7e06/dsdt.asl b/src/mainboard/msi/ms7e06/dsdt.asl
new file mode 100644
index 0000000000..11fd5e6528
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/dsdt.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0) {
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/alderlake/acpi/southbridge.asl>
+	}
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include "acpi/superio.asl"
+	}
+
+	#include "acpi/mainboard.asl"
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/msi/ms7e06/gpio.h b/src/mainboard/msi/ms7e06/gpio.h
new file mode 100644
index 0000000000..bf61dcb71a
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/gpio.h
@@ -0,0 +1,807 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+
+	/* GPP_I0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I0, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I1 - DDSP_HPD1 */
+	PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),
+	/* GPP_I2 - DDSP_HPD2 */
+	PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1),
+	/* GPP_I3 - DDSP_HPD3 */
+	PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1),
+	/* GPP_I4 - DDSP_HPD4 */
+	PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1),
+	/* GPP_I5 - DDPB_CTRLCLK */
+	PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1),
+	/* GPP_I6 - DDPB_CTRLDATA */
+	PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1),
+	/* GPP_I7 - DDPC_CTRLCLK */
+	PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1),
+	/* GPP_I8 - DDPC_CTRLDATA */
+	PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1),
+	/* GPP_I9 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I9, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I11 - USB_OC4# */
+	PAD_CFG_NF(GPP_I11, NONE, PLTRST, NF1),
+	/* GPP_I12 - USB_OC5# */
+	PAD_CFG_NF(GPP_I12, NONE, PLTRST, NF1),
+	/* GPP_I13 - USB_OC6# */
+	PAD_CFG_NF(GPP_I13, NONE, PLTRST, NF1),
+	/* GPP_I14 - USB_OC7# */
+	PAD_CFG_NF(GPP_I14, NONE, PLTRST, NF1),
+	/* GPP_I15 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I16 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I17 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I18 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I18, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I20 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I20, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I21 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, PLTRST, OFF, ACPI),
+	/* GPP_I22 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_R ------- */
+
+	/* GPP_R0 - HDA_BCLK */
+	PAD_CFG_NF(GPP_R0, NONE, PLTRST, NF1),
+	/* GPP_R1 - HDA_SYNC */
+	PAD_CFG_NF(GPP_R1, NONE, PLTRST, NF1),
+	/* GPP_R2 - HDA_SDO */
+	PAD_CFG_NF(GPP_R2, NONE, PLTRST, NF1),
+	/* GPP_R3 - HDA_SDI0 */
+	PAD_CFG_NF(GPP_R3, NONE, PLTRST, NF1),
+	/* GPP_R4 - HDA_RST# */
+	PAD_CFG_NF(GPP_R4, NONE, PLTRST, NF1),
+	/* GPP_R5 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R6 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R8 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R8, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R9 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R9, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R11, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R12 - DDP3_CTRLCLK */
+	PAD_CFG_NF(GPP_R12, NONE, PLTRST, NF2),
+	/* GPP_R13 - DDP3_CTRLDATA */
+	PAD_CFG_NF(GPP_R13, NONE, PLTRST, NF2),
+	/* GPP_R14 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R14, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R15 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R15, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R16 - DDP1_CTRLCLK */
+	PAD_CFG_NF(GPP_R16, NONE, PLTRST, NF1),
+	/* GPP_R17 - DDP1_CTRLDATA */
+	PAD_CFG_NF(GPP_R17, NONE, PLTRST, NF1),
+	/* GPP_R18 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R18, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R20 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R20, NONE, PLTRST, OFF, ACPI),
+	/* GPP_R21 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_R21, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_J ------- */
+
+	/* GPP_J0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J0, NONE, PLTRST, OFF, ACPI),
+	/* GPP_J1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J1, NONE, PLTRST, OFF, ACPI),
+	/* GPP_J2 - CNV_BRI_DT */
+	PAD_CFG_NF(GPP_J2, NONE, PLTRST, NF1),
+	/* GPP_J3 - CNV_BRI_RSP */
+	PAD_CFG_NF(GPP_J3, NONE, PLTRST, NF1),
+	/* GPP_J4 - CNV_RGI_DT */
+	PAD_CFG_NF(GPP_J4, NONE, PLTRST, NF1),
+	/* GPP_J5 - CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_J5, NONE, PLTRST, NF1),
+	/* GPP_J6 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J6, NONE, PLTRST, OFF, ACPI),
+	/* GPP_J7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J7, NONE, PLTRST, OFF, ACPI),
+	/* GPP_J8 - GPIO */
+	PAD_NC(GPP_J8, NONE),
+	/* GPP_J9 - SRCCLKREQ17# */
+	PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1),
+	/* GPP_J10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_J11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_J11, NONE, PLTRST, OFF, ACPI),
+
+	/* vGPIO controls certain features like CNVi, include the definitions as well */
+
+	/* ------- GPIO Group vGPIO ------- */
+	/* CNVi BT Enable, TX = 1 */
+	_PAD_CFG_STRUCT(VGPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
+	/* CNVi BT host wake */
+	_PAD_CFG_STRUCT(VGPIO_4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	/* CNVi BT on USB, TX = 1 */
+	_PAD_CFG_STRUCT(VGPIO_5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_BUF(RX_DISABLE) | 1, 0),
+	_PAD_CFG_STRUCT(VGPIO_6, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_7, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_8, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_9, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_TXD */
+	_PAD_CFG_STRUCT(VGPIO_11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_RXD */
+	_PAD_CFG_STRUCT(VGPIO_12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_CTS# */
+	_PAD_CFG_STRUCT(VGPIO_13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vCNV_MFUART1_RTS# */
+	_PAD_CFG_STRUCT(VGPIO_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_TXD */
+	_PAD_CFG_STRUCT(VGPIO_23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_RXD */
+	_PAD_CFG_STRUCT(VGPIO_24, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_CTS# */
+	_PAD_CFG_STRUCT(VGPIO_25, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),	/* vISH_UART0_RTS# */
+	_PAD_CFG_STRUCT(VGPIO_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+	_PAD_CFG_STRUCT(VGPIO_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),	/* GPIO */
+
+	/* ------- GPIO Group vGPIO_0 ------- */
+	/* These are Virtual USB OC pins */
+	_PAD_CFG_STRUCT(VGPIO_USB_0,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_0 */
+	_PAD_CFG_STRUCT(VGPIO_USB_1,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_1 */
+	_PAD_CFG_STRUCT(VGPIO_USB_2,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_2 */
+	_PAD_CFG_STRUCT(VGPIO_USB_3,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_3 */
+	_PAD_CFG_STRUCT(VGPIO_USB_8,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_8 */
+	_PAD_CFG_STRUCT(VGPIO_USB_9,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_9 */
+	_PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_10 */
+	_PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_11 */
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_B ------- */
+
+	/* GPP_B0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B0, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B1, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B2 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B5 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B6 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B8 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B9 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B11, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B12 - SLP_S0# */
+	PAD_CFG_NF(GPP_B12, NONE, PLTRST, NF1),
+	/* GPP_B13 - PLTRST# */
+	PAD_CFG_NF(GPP_B13, NONE, PLTRST, NF1),
+	/* GPP_B14 - SPKR */
+	PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),
+	/* GPP_B15 - GPIO */
+	PAD_CFG_GPO(GPP_B15, 0, PLTRST),
+	/* GPP_B16 - GPIO */
+	PAD_CFG_GPO(GPP_B16, 0, PLTRST),
+	/* GPP_B17 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B18 - PMCALERT# */
+	PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1),
+	/* GPP_B19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B20 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B21 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B22 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, PLTRST, OFF, ACPI),
+	/* GPP_B23 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_G ------- */
+
+	/* GPP_G0 - GPIO */
+	PAD_CFG_GPO(GPP_G0, 0, PLTRST),
+	/* GPP_G1 - GPIO */
+	PAD_CFG_GPO(GPP_G1, 1, RSMRST),
+	/* GPP_G2 - DNX_FORCE_RELOAD */
+	PAD_CFG_NF(GPP_G2, NONE, PLTRST, NF1),
+	/* GPP_G3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_G3, NONE, PLTRST, OFF, ACPI),
+	/* GPP_G4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_G4, NONE, PLTRST, OFF, ACPI),
+	/* GPP_G5 - SLP_DRAM# */
+	PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
+	/* GPP_G6 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI),
+	/* GPP_G7 - GPIO */
+	PAD_NC(GPP_G7, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+
+	/* GPP_H0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H0, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H2 - SRCCLKREQ8# */
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),
+	/* GPP_H3 - SRCCLKREQ9# */
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
+	/* GPP_H4 - SRCCLKREQ10# */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* GPP_H5 - GPIO */
+	PAD_NC(GPP_H5, NONE),
+	/* GPP_H6 - SRCCLKREQ12# */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* GPP_H7 - SRCCLKREQ13# */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* GPP_H8 - SRCCLKREQ14# */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	/* GPP_H9 - SRCCLKREQ15# */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	/* GPP_H10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H12 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H13 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H14 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H15 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H16 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H17 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H17, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H18 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_H20 - GPIO */
+	PAD_CFG_GPO(GPP_H20, 1, PLTRST),
+	/* GPP_H21 - GPIO */
+	PAD_CFG_GPO(GPP_H21, 0, PLTRST),
+	/* GPP_H22 - GPIO */
+	PAD_CFG_GPO(GPP_H22, 1, PLTRST),
+	/* GPP_H23 - GPIO */
+	PAD_CFG_GPO(GPP_H23, 1, PLTRST),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* ------- GPIO Group GPD ------- */
+
+	/* GPD0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPD0, NONE, PLTRST, OFF, ACPI),
+	/* GPD1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPD1, NONE, PLTRST, OFF, ACPI),
+	/* GPD2 - LAN_WAKE# */
+	PAD_CFG_NF(GPD2, NONE, PLTRST, NF1),
+	/* GPD3 - PWRBTN# */
+	PAD_CFG_NF(GPD3, NONE, PLTRST, NF1),
+	/* GPD4 - SLP_S3# */
+	PAD_CFG_NF(GPD4, NONE, PLTRST, NF1),
+	/* GPD5 - SLP_S4# */
+	PAD_CFG_NF(GPD5, NONE, PLTRST, NF1),
+	/* GPD6 - SLP_A# */
+	PAD_CFG_NF(GPD6, NONE, PLTRST, NF1),
+	/* GPD7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PLTRST, OFF, ACPI),
+	/* GPD8 - SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, PLTRST, NF1),
+	/* GPD9 - SLP_WLAN# */
+	PAD_CFG_NF(GPD9, NONE, PLTRST, NF1),
+	/* GPD10 - SLP_S5# */
+	PAD_CFG_NF(GPD10, NONE, PLTRST, NF1),
+	/* GPD11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPD11, NONE, PLTRST, OFF, ACPI),
+	/* GPD12 - GPIO */
+	PAD_CFG_TERM_GPO(GPD12, 1, DN_5K, RSMRST),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+
+	/* GPP_A0 - ESPI_IO0 */
+	PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1),
+	/* GPP_A1 - ESPI_IO1 */
+	PAD_CFG_NF(GPP_A1, NONE, PLTRST, NF1),
+	/* GPP_A2 - ESPI_IO2 */
+	PAD_CFG_NF(GPP_A2, NONE, PLTRST, NF1),
+	/* GPP_A3 - ESPI_IO3 */
+	PAD_CFG_NF(GPP_A3, NONE, PLTRST, NF1),
+	/* GPP_A4 - ESPI_CS0# */
+	PAD_CFG_NF(GPP_A4, NONE, PLTRST, NF1),
+	/* GPP_A5 - ESPI_CLK */
+	PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),
+	/* GPP_A6 - ESPI_RESET# */
+	PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1),
+	/* GPP_A7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
+	/* GPP_A8 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A8, NONE, PLTRST, OFF, ACPI),
+	/* GPP_A9 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A9, NONE, PLTRST, OFF, ACPI),
+	/* GPP_A10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_A11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, PLTRST, OFF, ACPI),
+	/* GPP_A12 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, PLTRST, OFF, ACPI),
+	/* GPP_A13 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A13, NONE, PLTRST, OFF, ACPI),
+	/* GPP_A14 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_C ------- */
+
+	/* GPP_C0 - SMBCLK */
+	PAD_CFG_NF(GPP_C0, NONE, PLTRST, NF1),
+	/* GPP_C1 - SMBDATA */
+	PAD_CFG_NF(GPP_C1, NONE, PLTRST, NF1),
+	/* GPP_C2 - SMBALERT# */
+	PAD_CFG_NF(GPP_C2, NONE, PLTRST, NF1),
+	/* GPP_C3 - GPIO */
+	PAD_CFG_GPO(GPP_C3, 1, PLTRST),
+	/* GPP_C4 - GPIO */
+	PAD_CFG_GPO(GPP_C4, 1, PLTRST),
+	/* GPP_C5 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C6 - GPIO */
+	PAD_CFG_GPO(GPP_C6, 0, PLTRST),
+	/* GPP_C7 - GPIO */
+	PAD_CFG_GPO(GPP_C7, 0, PLTRST),
+	/* GPP_C8 - GPIO */
+	PAD_CFG_GPO(GPP_C8, 1, RSMRST),
+	/* GPP_C9 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C9, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C11, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C12 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C12, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C13 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C13, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C14 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C14, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C15 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C16 - I2C0_SDA */
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+	/* GPP_C17 - I2C0_SCL */
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+	/* GPP_C18 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C20 - GPIO */
+	PAD_CFG_GPO(GPP_C20, 0, PLTRST),
+	/* GPP_C21 - GPIO */
+	PAD_CFG_GPO(GPP_C21, 0, PLTRST),
+	/* GPP_C22 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C22, NONE, PLTRST, OFF, ACPI),
+	/* GPP_C23 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, PLTRST, OFF, ACPI),
+
+	/* CPU PCIe CLKREQ virtual wire message buses */
+	_PAD_CFG_STRUCT(VGPIO_PCIE_0,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_1,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_2,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_3,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_4,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_5,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_6,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_7,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_8,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_9,  PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0),
+
+	/* ------- GPIO Community 4 ------- */
+
+	/* ------- GPIO Group GPP_S ------- */
+
+	/* GPP_S0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, PLTRST, OFF, ACPI),
+	/* GPP_S1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, PLTRST, OFF, ACPI),
+	/* GPP_S2 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, PLTRST, OFF, ACPI),
+	/* GPP_S3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, PLTRST, OFF, ACPI),
+	/* GPP_S4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, PLTRST, OFF, ACPI),
+	/* GPP_S5 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_S6 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, PLTRST, OFF, ACPI),
+	/* GPP_S7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_E ------- */
+
+	/* GPP_E0 - SATAXPCIE0 */
+	PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1),
+	/* GPP_E1 - SATAXPCIE1 */
+	PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1),
+	/* GPP_E2 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E5 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E6 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E8 - SATALED# */
+	PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1),
+	/* GPP_E9 - USB_OC0# */
+	PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF1),
+	/* GPP_E10 - USB_OC1# */
+	PAD_CFG_NF(GPP_E10, NONE, PLTRST, NF1),
+	/* GPP_E11 - USB_OC2# */
+	PAD_CFG_NF(GPP_E11, NONE, PLTRST, NF1),
+	/* GPP_E12 - USB_OC3# */
+	PAD_CFG_NF(GPP_E12, NONE, PLTRST, NF1),
+	/* GPP_E13 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E14 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E15 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E16 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E17 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E18 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E20 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E20, NONE, PLTRST, OFF, ACPI),
+	/* GPP_E21 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E21, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_K ------- */
+
+	/* GPP_K0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K0, NONE, PLTRST, OFF, ACPI),
+	/* GPP_K1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K1, NONE, PLTRST, OFF, ACPI),
+	/* GPP_K2 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K2, NONE, PLTRST, OFF, ACPI),
+	/* GPP_K3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K3, NONE, PLTRST, OFF, ACPI),
+	/* GPP_K4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K4, NONE, PLTRST, OFF, ACPI),
+	/* GPP_K5 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_K6 - n/a */
+	PAD_CFG_NF(GPP_K6, UP_20K, DEEP, NF2),
+	/* GPP_K7 - n/a */
+	PAD_CFG_NF(GPP_K7, DN_20K, DEEP, NF2),
+	/* GPP_K8 - CORE_VID0 */
+	PAD_CFG_NF(GPP_K8, NONE, PLTRST, NF1),
+	/* GPP_K9 - CORE_VID1 */
+	PAD_CFG_NF(GPP_K9, NONE, PLTRST, NF1),
+	/* GPP_K10 - n/a */
+	PAD_CFG_NF(GPP_K10, UP_20K, DEEP, NF2),
+	/* GPP_K11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_K11, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_F ------- */
+
+	/* GPP_F0 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F0, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F1 - GPIO */
+	PAD_CFG_GPI_SCI(GPP_F1, NONE, PLTRST, EDGE_SINGLE, INVERT),
+	/* GPP_F2 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F4 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F5 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F6 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F6, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F8 - SATA_DEVSLP6 */
+	PAD_CFG_NF(GPP_F8, NONE, PLTRST, NF1),
+	/* GPP_F9 - SATA_DEVSLP7 */
+	PAD_CFG_NF(GPP_F9, NONE, PLTRST, NF1),
+	/* GPP_F10 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F12 - GPIO */
+	PAD_CFG_GPO(GPP_F12, 1, RSMRST),
+	/* GPP_F13 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F14 - PS_ON# */
+	PAD_CFG_NF(GPP_F14, NONE, PLTRST, NF1),
+	/* GPP_F15 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F16 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F17 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F18 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F18, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F20 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F20, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F21 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F22 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F22, NONE, PLTRST, OFF, ACPI),
+	/* GPP_F23 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Community 5 ------- */
+
+	/* ------- GPIO Group GPP_D ------- */
+
+	/* GPP_D0 - SRCCLKREQ0# */
+	PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+	/* GPP_D1 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D2 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D3 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D4 - SML1CLK */
+	PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
+	/* GPP_D5 - CNV_RF_RESET# */
+	PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF2),
+	/* GPP_D6 - MODEM_CLKREQ */
+	PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF3),
+	/* GPP_D7 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D8 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D9 - SML0CLK */
+	PAD_CFG_NF(GPP_D9, NONE, PLTRST, NF1),
+	/* GPP_D10 - SML0DATA */
+	PAD_CFG_NF(GPP_D10, NONE, PLTRST, NF1),
+	/* GPP_D11 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D12 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D13 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D14 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D15 - SML1DATA */
+	PAD_CFG_NF(GPP_D15, NONE, PLTRST, NF1),
+	/* GPP_D16 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D17 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D18 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D19 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D20 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D21 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D21, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D22 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, PLTRST, OFF, ACPI),
+	/* GPP_D23 - GPIO */
+	PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI),
+};
+
+static const struct pad_config clkreq_disabled_table[] = {
+	/* GPP_J9 - SRCCLKREQ17# */
+	PAD_NC(GPP_J9, NONE),
+	/* GPP_H2 - SRCCLKREQ8# */
+	PAD_NC(GPP_H2, NONE),
+	/* GPP_H3 - SRCCLKREQ9# */
+	PAD_NC(GPP_H3, NONE),
+	/* GPP_H4 - SRCCLKREQ10# */
+	PAD_NC(GPP_H4, NONE),
+	/* GPP_H6 - SRCCLKREQ12# */
+	PAD_NC(GPP_H6, NONE),
+	/* GPP_H7 - SRCCLKREQ13# */
+	PAD_NC(GPP_H7, NONE),
+	/* GPP_H8 - SRCCLKREQ14# */
+	PAD_NC(GPP_H8, NONE),
+	/* GPP_H9 - SRCCLKREQ15# */
+	PAD_NC(GPP_H9, NONE),
+	/* GPP_D0 - SRCCLKREQ0# */
+	PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
+
+	/* CPU PCIe CLKREQ virtual wire message buses */
+	_PAD_CFG_STRUCT(VGPIO_PCIE_0,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_1,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_2,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_3,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_4,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_5,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_6,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_7,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_8,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_9,  PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_10, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_11, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_12, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_13, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_14, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_64, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_65, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_66, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_17, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_20, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_23, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_24, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_26, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_28, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_29, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_30, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_31, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_68, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_69, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_70, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_71, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_32, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_34, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_35, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_36, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_37, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_39, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_40, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_41, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_42, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_43, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_44, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_45, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_46, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_47, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_72, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_73, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_74, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_75, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+
+	_PAD_CFG_STRUCT(VGPIO_PCIE_48, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_49, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_50, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_51, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_52, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_53, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_54, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_55, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_56, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_57, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_58, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_59, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_60, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_62, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_63, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_76, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_77, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_78, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+	_PAD_CFG_STRUCT(VGPIO_PCIE_79, PAD_FUNC(GPIO) | PAD_RESET(DEEP), 0),
+};
diff --git a/src/mainboard/msi/ms7e06/hda_verb.c b/src/mainboard/msi/ms7e06/hda_verb.c
new file mode 100644
index 0000000000..90ca604b7a
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/hda_verb.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek ALC897 */
+	0x10ec0897, /* Vendor ID */
+	0x14629e06, /* Subsystem ID */
+	15, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x14629e06),
+	AZALIA_PIN_CFG(0, 0x11, 0x4037d540),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19040),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214020),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x402af66b),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	/* Alderlake HDMI */
+	0x80862818, /* Vendor ID */
+	0x80860101, /* Subsystem ID */
+	2, /* Number of entries */
+	AZALIA_SUBVENDOR(2, 0x80860101),
+	AZALIA_PIN_CFG(2, 0x04, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x06, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x08, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0a, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0b, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0c, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0d, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0e, 0x18560010),
+	AZALIA_PIN_CFG(2, 0x0f, 0x18560010),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/msi/ms7e06/mainboard.c b/src/mainboard/msi/ms7e06/mainboard.c
new file mode 100644
index 0000000000..a80b240145
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/mainboard.c
@@ -0,0 +1,535 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <device/device.h>
+#include <identity.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <smbios.h>
+#include <string.h>
+
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->preferred_pm_profile = PM_DESKTOP;
+	fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+}
+
+static void mainboard_init(void *chip_info)
+{
+
+}
+
+u8 smbios_mainboard_feature_flags(void)
+{
+	return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
+}
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}
+
+const char *smbios_system_product_name(void)
+{
+	return "MS-7E06";
+}
+
+const char *smbios_mainboard_product_name(void)
+{
+	if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) {
+		if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI))
+			return "PRO Z790-P WIFI DDR4(MS-7E06)";
+		else
+			return "PRO Z790-P DDR4(MS-7E06)";
+	}
+
+	if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI)) {
+		if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI))
+			return "PRO Z790-P WIFI (MS-7E06)";
+		else
+			return "PRO Z790-P (MS-7E06)";
+	}
+
+	return CONFIG_MAINBOARD_PART_NUMBER;
+}
+
+/* Only baseboard serial number is populated */
+const char *smbios_system_serial_number(void)
+{
+	return "Default string";
+}
+
+const char *smbios_system_sku(void)
+{
+	return "Default string";
+}
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	uint8_t aspm, aspm_l1;
+
+	if (CONFIG(PCIEXP_L1_SUB_STATE) && CONFIG(PCIEXP_CLK_PM))
+		aspm_l1 = 2; // 2 - L1.1 and L1.2
+	else
+		aspm_l1 = 0;
+
+	if (CONFIG(PCIEXP_ASPM)) {
+		aspm = CONFIG(PCIEXP_L1_SUB_STATE) ? 3 : 1; // 3 - L0sL1, 1 - L0s
+	} else {
+		aspm = 0;
+		aspm_l1 = 0;
+	}
+
+	memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm));
+	memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm));
+	memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating));
+	memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating));
+
+	params->UsbPdoProgramming = 1;
+	params->CpuPcieFiaProgramming = 1;
+	params->PcieRpFunctionSwap = 0;
+	params->CpuPcieRpFunctionSwap = 0;
+	params->PchLegacyIoLowLatency = 1;
+	params->PchDmiAspmCtrl = 0;
+
+	params->CpuPcieRpPmSci[0] = 0; // M2_1
+	params->CpuPcieRpPmSci[1] = 0; // PCI_E1
+	params->PcieRpPmSci[0]    = 0; // PCI_E2
+	params->PcieRpPmSci[1]    = 0; // PCI_E4
+	params->PcieRpPmSci[2]    = 0; // Ethernet
+	params->PcieRpPmSci[4]    = 0; // PCI_E3
+	params->PcieRpPmSci[8]    = 0; // M2_3
+	params->PcieRpPmSci[20]   = 0; // M2_4
+	params->PcieRpPmSci[24]   = 0; // M2_2
+
+	params->PcieRpMaxPayload[0]  = 1; // PCI_E2
+	params->PcieRpMaxPayload[1]  = 1; // PCI_E4
+	params->PcieRpMaxPayload[2]  = 1; // Ethernet
+	params->PcieRpMaxPayload[4]  = 1; // PCI_E3
+	params->PcieRpMaxPayload[8]  = 1; // M2_3
+	params->PcieRpMaxPayload[20] = 1; // M2_4
+	params->PcieRpMaxPayload[24] = 1; // M2_2
+
+	params->CpuPcieRpTransmitterHalfSwing[0] = 1; // M2_1
+	params->CpuPcieRpTransmitterHalfSwing[1] = 1; // PCI_E1
+	params->PcieRpTransmitterHalfSwing[0]    = 1; // PCI_E2
+	params->PcieRpTransmitterHalfSwing[1]    = 1; // PCI_E4
+	params->PcieRpTransmitterHalfSwing[2]    = 1; // Ethernet
+	params->PcieRpTransmitterHalfSwing[4]    = 1; // PCI_E3
+	params->PcieRpTransmitterHalfSwing[8]    = 1; // M2_3
+	params->PcieRpTransmitterHalfSwing[20]   = 1; // M2_4
+	params->PcieRpTransmitterHalfSwing[24]   = 1; // M2_2
+
+	params->CpuPcieRpEnableCpm[0] = CONFIG(PCIEXP_CLK_PM); // M2_1
+	params->CpuPcieRpEnableCpm[1] = CONFIG(PCIEXP_CLK_PM); // PCI_E1
+	params->PcieRpEnableCpm[0]    = CONFIG(PCIEXP_CLK_PM); // PCI_E2
+	params->PcieRpEnableCpm[1]    = CONFIG(PCIEXP_CLK_PM); // PCI_E4
+	params->PcieRpEnableCpm[4]    = CONFIG(PCIEXP_CLK_PM); // PCI_E3
+	params->PcieRpEnableCpm[8]    = CONFIG(PCIEXP_CLK_PM); // M2_3
+	params->PcieRpEnableCpm[20]   = CONFIG(PCIEXP_CLK_PM); // M2_4
+	params->PcieRpEnableCpm[24]   = CONFIG(PCIEXP_CLK_PM); // M2_2
+
+	params->CpuPcieRpL1Substates[0] = aspm_l1; // M2_1
+	params->CpuPcieRpL1Substates[1] = aspm_l1; // PCI_E1
+	params->PcieRpL1Substates[0]    = aspm_l1; // PCI_E2
+	params->PcieRpL1Substates[1]    = aspm_l1; // PCI_E4
+	params->PcieRpL1Substates[4]    = aspm_l1; // PCI_E3
+	params->PcieRpL1Substates[8]    = aspm_l1; // M2_3
+	params->PcieRpL1Substates[20]   = aspm_l1; // M2_4
+	params->PcieRpL1Substates[24]   = aspm_l1; // M2_2
+
+	params->CpuPcieRpAspm[0] = aspm; // M2_1
+	params->CpuPcieRpAspm[1] = aspm; // PCI_E1
+	params->PcieRpAspm[0]    = aspm; // PCI_E2
+	params->PcieRpAspm[1]    = aspm; // PCI_E4
+	params->PcieRpAspm[4]    = aspm; // PCI_E3
+	params->PcieRpAspm[8]    = aspm; // M2_3
+	params->PcieRpAspm[20]   = aspm; // M2_4
+	params->PcieRpAspm[24]   = aspm; // M2_2
+
+	params->PcieRpAcsEnabled[0]  = 1; // PCI_E2
+	params->PcieRpAcsEnabled[1]  = 1; // PCI_E4
+	params->PcieRpAcsEnabled[2]  = 1; // Ethernet
+	params->PcieRpAcsEnabled[4]  = 1; // PCI_E3
+	params->PcieRpAcsEnabled[8]  = 1; // M2_3
+	params->PcieRpAcsEnabled[20] = 1; // M2_4
+	params->PcieRpAcsEnabled[24] = 1; // M2_2
+
+	params->CpuPcieClockGating[0] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPciePowerGating[0] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPcieRpMultiVcEnabled[0] = 1;
+	params->CpuPcieRpPeerToPeerMode[0] = 1;
+	params->CpuPcieRpMaxPayload[0] = 2; // 512B
+	params->CpuPcieRpAcsEnabled[0] = 1;
+
+	params->CpuPcieClockGating[1] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPciePowerGating[1] = CONFIG(PCIEXP_CLK_PM);
+	params->CpuPcieRpPeerToPeerMode[1] = 1;
+	params->CpuPcieRpMaxPayload[1] = 2; // 512B
+	params->CpuPcieRpAcsEnabled[1] = 1;
+
+	params->SataPortsSolidStateDrive[6] = 1; // M2_3
+	params->SataPortsSolidStateDrive[7] = 1; // M2_4
+	params->SataLedEnable = 1;
+}
+
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+static const struct port_information smbios_type8_info[] = {
+	{
+		.internal_reference_designator = "PS2_USB1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "Keyboard",
+		.external_connector_type       = CONN_PS_2,
+		.port_type                     = TYPE_KEYBOARD_PORT
+	},
+	{
+		.internal_reference_designator = "PS2_USB1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "PS2Mouse",
+		.external_connector_type       = CONN_PS_2,
+		.port_type                     = TYPE_MOUSE_PORT
+	},
+	{
+		.internal_reference_designator = "PS2_USB1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 2.0 Type-A",
+		.external_connector_type       = CONN_ACCESS_BUS_USB,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "PS2_USB1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 2.0 Type-A (Flash BIOS)",
+		.external_connector_type       = CONN_ACCESS_BUS_USB,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "JTPM1 - TPM HDR",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "LAN_USB1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "Ethernet",
+		.external_connector_type       = CONN_RJ_45,
+		.port_type                     = TYPE_NETWORK_PORT
+	},
+	{
+		.internal_reference_designator = "LAN_USB1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 3.2 Gen2x2 Type-C",
+		.external_connector_type       = CONN_USB_TYPE_C,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "LAN_USB1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 3.2 Gen2 Type-A",
+		.external_connector_type       = CONN_ACCESS_BUS_USB,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "SATA1",
+		.internal_connector_type       = CONN_SAS_SATA,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_SATA
+	},
+	{
+		.internal_reference_designator = "SATA2",
+		.internal_connector_type       = CONN_SAS_SATA,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_SATA
+	},
+	{
+		.internal_reference_designator = "SATA3",
+		.internal_connector_type       = CONN_SAS_SATA,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_SATA
+	},
+	{
+		.internal_reference_designator = "SATA4",
+		.internal_connector_type       = CONN_SAS_SATA,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_SATA
+	},
+	{
+		.internal_reference_designator = "SATA5",
+		.internal_connector_type       = CONN_SAS_SATA,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_SATA
+	},
+	{
+		.internal_reference_designator = "SATA6",
+		.internal_connector_type       = CONN_SAS_SATA,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_SATA
+	},
+	{
+		.internal_reference_designator = "JTBT1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_THUNDERBOLT
+	},
+	{
+		.internal_reference_designator = "JC1 - CHASSIS INTRUSION",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "JAUD1 - FRONT AUDIO",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_AUDIO_PORT
+	},
+	{
+		.internal_reference_designator = "AUDIO1 - REAR AUDIO",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "Audio",
+		.external_connector_type       = CONN_OTHER,
+		.port_type                     = TYPE_AUDIO_PORT
+	},
+	{
+		.internal_reference_designator = "JFP1 - FRONT PANEL",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "JFP2 - PC SPEAKER",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "JBAT1 - CLEAR CMOS",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "JDASH1 - TUNING CONTROLLER",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "JRGB1 - 5050 RGB LED",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "JRAINBOW1 - WS2812B RGB LED",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "JRAINBOW2 - WS2812B RGB LED",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "CPU_FAN1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "PUMP_FAN1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "SYS_FAN1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "SYS_FAN2",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "SYS_FAN3",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "SYS_FAN4",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "SYS_FAN5",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "SYS_FAN6",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "DP_HDMI1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "HDMI",
+		.external_connector_type       = CONN_OTHER,
+		.port_type                     = TYPE_VIDEO_PORT
+	},
+	{
+		.internal_reference_designator = "DP_HDMI1",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "Display Port",
+		.external_connector_type       = CONN_OTHER,
+		.port_type                     = TYPE_VIDEO_PORT
+	},
+	{
+		.internal_reference_designator = "USB2",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 2.0 Type-A (Upper)",
+		.external_connector_type       = CONN_ACCESS_BUS_USB,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "USB2",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 2.0 Type-A (Lower)",
+		.external_connector_type       = CONN_ACCESS_BUS_USB,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "USB2",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 3.2 Gen1 Type-A (Upper)",
+		.external_connector_type       = CONN_ACCESS_BUS_USB,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "USB2",
+		.internal_connector_type       = CONN_NONE,
+		.external_reference_designator = "USB 3.2 Gen1 Type-A (Lower)",
+		.external_connector_type       = CONN_ACCESS_BUS_USB,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "JUSB1 - USB 2.0 ",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "JUSB2 - USB 2.0",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "JUSB3 - USB 3.2 GEN 1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "JUSB4 - USB 3.2 GEN 1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "JUSB5 - USB-C",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_USB
+	},
+	{
+		.internal_reference_designator = "ATX_PWR1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "CPU_PWR1",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+	{
+		.internal_reference_designator = "CPU_PWR2",
+		.internal_connector_type       = CONN_OTHER,
+		.external_reference_designator = "",
+		.external_connector_type       = CONN_NONE,
+		.port_type                     = TYPE_OTHER_PORT
+	},
+};
+
+static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current)
+{
+	int len = 0;
+
+	// add port information
+	len += smbios_write_type8(
+		current, handle,
+		smbios_type8_info,
+		ARRAY_SIZE(smbios_type8_info)
+		);
+
+	return len;
+}
+#endif
+
+static void mainboard_enable(struct device *dev)
+{
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+	dev->ops->get_smbios_data = mainboard_smbios_data;
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/msi/ms7e06/romstage_fsp_params.c b/src/mainboard/msi/ms7e06/romstage_fsp_params.c
new file mode 100644
index 0000000000..d3c3c50fb0
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/romstage_fsp_params.c
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+#include <string.h>
+
+#include "gpio.h"
+
+#define FSP_CLK_NOTUSED			0xFF
+#define FSP_CLK_FREE_RUNNING		0x80
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+	/* According to DOC #573387 rcomp values no longer have to be provided */
+	/* DDR DIMM configuration does not need to set DQ/DQS maps */
+	.UserBd = BOARD_TYPE_DESKTOP_2DPC,
+
+	.ddr_config = {
+		.dq_pins_interleaved = true,
+	},
+};
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.ect = true, /* Early Command Training */
+
+	/* According to DOC #573387 rcomp values no longer have to be provided */
+	/* DDR DIMM configuration does not need to set DQ/DQS maps */
+	.UserBd = BOARD_TYPE_DESKTOP_2DPC,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = true,
+	},
+};
+
+static const struct mem_spd dimm_module_spd_info = {
+	.topo = MEM_TOPO_DIMM_MODULE,
+	.smbus = {
+		[0] = {
+			.addr_dimm[0] = 0x50,
+			.addr_dimm[1] = 0x51,
+		},
+		[1] = {
+			.addr_dimm[0] = 0x52,
+			.addr_dimm[1] = 0x53,
+		},
+	},
+};
+
+static void disable_pcie_clock_requests(FSP_M_CONFIG *m_cfg)
+{
+	memset(m_cfg->PcieClkSrcUsage, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcUsage));
+	memset(m_cfg->PcieClkSrcClkReq, FSP_CLK_NOTUSED, sizeof(m_cfg->PcieClkSrcClkReq));
+
+	m_cfg->PcieClkSrcUsage[0]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[8]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[9]  = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[10] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[12] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[13] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[14] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[15] = FSP_CLK_FREE_RUNNING;
+	m_cfg->PcieClkSrcUsage[17] = FSP_CLK_FREE_RUNNING;
+
+	gpio_configure_pads(clkreq_disabled_table, ARRAY_SIZE(clkreq_disabled_table));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = CONFIG(PCIEXP_CLK_PM);
+	memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented
+	memupd->FspmConfig.DmiAspm = 0;
+	memupd->FspmConfig.DmiAspmCtrl = 0;
+	memupd->FspmConfig.SkipExtGfxScan = 0;
+
+	memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	memupd->FspmConfig.PchHdaSdiEnable[0] = 1;
+
+	memupd->FspmConfig.MmioSize = 0xb00; /* 2.75GB in MB */
+
+	if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4))
+		memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false);
+	if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI))
+		memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false);
+
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+	if (!CONFIG(PCIEXP_CLK_PM))
+		disable_pcie_clock_requests(&memupd->FspmConfig);
+}
diff --git a/src/mainboard/msi/ms7e06/vboot-rwab.fmd b/src/mainboard/msi/ms7e06/vboot-rwab.fmd
new file mode 100644
index 0000000000..665c8949bb
--- /dev/null
+++ b/src/mainboard/msi/ms7e06/vboot-rwab.fmd
@@ -0,0 +1,49 @@
+FLASH 32M {
+	SI_ALL 4M {
+		SI_DESC 4K
+		SI_ME
+	}
+
+	UNUSED 12M
+
+	RW_MISC 320K {
+		UNIFIED_MRC_CACHE(PRESERVE) {
+			RECOVERY_MRC_CACHE 128K
+			RW_MRC_CACHE 128K
+		}
+		RW_ELOG(PRESERVE) 16K
+		RW_SHARED 16K {
+			SHARED_DATA 8K
+			VBLOCK_DEV 8K
+		}
+		RW_VPD(PRESERVE) 8K
+		RW_NVRAM(PRESERVE) 24K
+	}
+
+	CONSOLE 128K
+	SMMSTORE(PRESERVE) 256K
+	HSPHY_FW(PRESERVE) 32K
+
+	RW_SECTION_A 5264K {
+		VBLOCK_A 64K
+		FW_MAIN_A(CBFS)
+		RW_FWID_A 0x100
+	}
+
+	RW_SECTION_B 5264K {
+		VBLOCK_B 64K
+		FW_MAIN_B(CBFS)
+		RW_FWID_B 0x100
+	}
+
+	WP_RO 5M {
+		RO_VPD(PRESERVE) 16K
+		RO_SECTION {
+			FMAP 2K
+			RO_FRID 0x100
+			RO_FRID_PAD 0x700
+			GBB 12K
+			COREBOOT(CBFS)
+		}
+	}
+}