diff options
| author | Peter Lemenkov <lemenkov@gmail.com> | 2019-12-09 11:23:37 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 15:16:57 +0000 |
| commit | b8de01583531a758eb87c910417e2dfb89975ac2 (patch) | |
| tree | cb86b3aa6dbd7d3dbdbb0e8c4b33455d05dab654 /src | |
| parent | 07e78649e3d297f761dec44b1b407da205af4830 (diff) | |
mb/lenovo/t431s/devicetree: Rebalance against t430s one
Change-Id: Iec40dd20c87b97dbd81ba3c63486cb5e66d99dc6
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37600
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e3388de581..ae95e6c8d6 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -15,17 +15,14 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x17aa 0x2208 inherit - device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Integrated Graphics Controller + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock) register "sata_port_map" = "0x13" # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 14.0 on end # USB 3.0 Controller - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller + device pci 1c.0 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" @@ -33,10 +30,7 @@ chip northbridge/intel/sandybridge device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip ec/lenovo/h8 register "config0" = "0xa6" @@ -47,8 +41,6 @@ chip northbridge/intel/sandybridge register "has_bdc_detection" = "0" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on end # SMBus Controller device pci 1f.6 off end # Thermal end end |