Add support for the Mitac 6513WU mainboard, a Compaq OEM board using the

i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.

Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.

Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 433 insertions, 0 deletions

diff --git a/src/mainboard/mitac/6513wu/Config.lb b/src/mainboard/mitac/6513wu/Config.lb
new file mode 100644
index 0000000000..5c9a63fe1f
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/Config.lb
@@ -0,0 +1,142 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+arch i386 end
+driver mainboard.o
+if CONFIG_HAVE_PIRQ_TABLE
+	object irq_tables.o
+end
+makerule ./failover.E
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
+	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
+	action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
+	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
+	action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if CONFIG_USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i82810           # Northbridge
+  device apic_cluster 0 on              # APIC cluster
+    chip cpu/intel/socket_PGA370        # CPU
+      device apic 0 on end              # APIC
+    end
+  end
+  device pci_domain 0 on                # PCI domain
+    device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
+    chip drivers/pci/onboard
+      device pci 1.0 on end
+      register "rom_address" = "0xfff80000" # 512 KB image
+    end
+    chip southbridge/intel/i82801xx     # Southbridge
+      register "pirqa_routing" = "0x03"
+      register "pirqb_routing" = "0x05"
+      register "pirqc_routing" = "0x09"
+      register "pirqd_routing" = "0x0b"
+
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1e.0 on                # PCI bridge
+        device pci 5.0 on end           # Audio controller (ESS ES1988)
+      end
+      device pci 1f.0 on                # ISA bridge
+        chip superio/smsc/smscsuperio   # Super I/O (SMSC LPC47U332)
+          device pnp 4e.0 on            # Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 4e.3 on            # Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 4e.4 on            # COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 4e.5 on            # MIDI port (MPU-401)
+            io 0x60 = 0x330
+            irq 0x70 = 10
+          end
+          device pnp 4e.7 on            # PS/2 keyboard / mouse
+            io 0x60 = 0x60              # XXX: not relocatable
+            io 0x62 = 0x64              # XXX: not relocatable
+            irq 0x70 = 1                # PS/2 keyboard interrupt
+            irq 0x72 = 12               # PS/2 mouse interrupt
+          end
+          device pnp 4e.9 on            # Game port
+            io 0x60 = 0x201
+          end
+          device pnp 4e.a on            # Runtime registers
+            io 0x60 = 0x400
+          end
+          device pnp 4e.b off end       # SMBus
+        end
+      end
+      device pci 1f.1 on end            # IDE
+      device pci 1f.2 on end            # USB
+      device pci 1f.3 on end            # SMbus
+      device pci 1f.5 off end           # Audio controller
+      device pci 1f.6 off end           # Modem
+    end
+  end
+end
diff --git a/src/mainboard/mitac/6513wu/Options.lb b/src/mainboard/mitac/6513wu/Options.lb
new file mode 100644
index 0000000000..c065c5887f
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/Options.lb
@@ -0,0 +1,110 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses CC
+uses CONFIG_CBFS
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_OBJCOPY
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_RAMBASE
+uses CONFIG_ROMBASE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_ROM_SECTION_OFFSET
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_STACK_SIZE
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_XIP_ROM_SIZE
+uses COREBOOT_EXTRA_VERSION
+uses HOSTCC
+
+# Motherboard info, tables, etc.
+default CONFIG_MAINBOARD_VENDOR = "Mitac"
+default CONFIG_MAINBOARD_PART_NUMBER = "6513WU"
+default CONFIG_IRQ_SLOT_COUNT = 8
+default CONFIG_HAVE_PIRQ_TABLE = 1
+default CONFIG_HAVE_MP_TABLE = 0
+default CONFIG_HAVE_OPTION_TABLE = 0
+default CONFIG_USE_OPTION_TABLE = 0
+
+# ROM layout
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
+default CONFIG_FALLBACK_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_ROM_PAYLOAD = 1
+default CONFIG_CBFS = 0
+
+# RAM layout
+default CONFIG_RAMBASE = 0x00004000
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 16 * 1024
+
+# Misc. settings
+default CONFIG_USE_INIT = 0
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_UDELAY_TSC = 1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
+
+# Compiler setup
+default CONFIG_CROSS_COMPILE = ""
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+
+# Console settings
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3     # 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 7  # No debugging/spew
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
+
+# Enable onboard video
+default CONFIG_CONSOLE_VGA = 1
+default CONFIG_PCI_ROM_RUN = 1
+
+end
diff --git a/src/mainboard/mitac/6513wu/auto.c b/src/mainboard/mitac/6513wu/auto.c
new file mode 100644
index 0000000000..55cc3fe2ac
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/auto.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"
+#include "northbridge/intel/i82810/raminit.h"
+#include "lib/debug.c"
+#include "pc80/udelay_io.c"
+#include "lib/delay.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+	return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i82810/raminit.c"
+/* #include "northbridge/intel/i82810/debug.c" */
+
+static void main(unsigned long bist)
+{
+	if (bist == 0)
+		early_mtrr_init();
+
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();
+
+	report_bist_failure(bist);
+	enable_smbus();
+	/* dump_spd_registers(); */
+	sdram_set_registers();
+	sdram_set_spd_registers();
+	sdram_enable();
+	/* ram_check(0, 640 * 1024); */
+}
diff --git a/src/mainboard/mitac/6513wu/chip.h b/src/mainboard/mitac/6513wu/chip.h
new file mode 100644
index 0000000000..0421977d24
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/mitac/6513wu/irq_tables.c b/src/mainboard/mitac/6513wu/irq_tables.c
new file mode 100644
index 0000000000..5df20ba644
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/irq_tables.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+/*
+ * Each of PIRQA..D can be routed to IRQ 3-7, 9-12, 14, or 15; but the
+ * selected IRQs can't be shared with ISA devices (Intel DS 290655-003,
+ * section 5.7.6).
+ *
+ * Correspondingly, the IRQs used on the Super I/O (4,6,7,10,12) are
+ * excluded from the masks, leaving 0xca28 (3,5,9,11,14,15).
+ */
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,         /* u32 signature */
+	PIRQ_VERSION,           /* u16 version */
+	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,                   /* Interrupt router bus */
+	(0x1f << 3) | 0x0,      /* Interrupt router dev */
+	0,                      /* IRQs devoted exclusively to PCI usage */
+	0x8086,                 /* Vendor */
+	0x7000,                 /* Device */
+	0,                      /* Miniport */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xb6,                   /* Checksum (has to be set to some value that
+	                         * would give 0 after the sum of all bytes
+	                         * for this structure (including checksum).
+	                         */
+	{
+		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+		{0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x61, 0xca28}, {0x00, 0x0000}, {0x63, 0xca28}}, 0x0, 0x0},
+		{0x00, (0x1e << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x0, 0x0},
+		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x01, (0x05 << 3) | 0x0, {{0x63, 0xca28}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+		{0x01, (0x08 << 3) | 0x0, {{0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}}, 0x1, 0x0},
+		{0x01, (0x09 << 3) | 0x0, {{0x61, 0xca28}, {0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}}, 0x2, 0x0},
+		{0x01, (0x0a << 3) | 0x0, {{0x62, 0xca28}, {0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}}, 0x3, 0x0},
+		{0x01, (0x0b << 3) | 0x0, {{0x63, 0xca28}, {0x60, 0xca28}, {0x61, 0xca28}, {0x62, 0xca28}}, 0x4, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/mitac/6513wu/mainboard.c b/src/mainboard/mitac/6513wu/mainboard.c
new file mode 100644
index 0000000000..7d5e19d088
--- /dev/null
+++ b/src/mainboard/mitac/6513wu/mainboard.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Mitac 6513WU Mainboard")
+};
diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c
index 22d8e25e53..148eeab8aa 100644
--- a/src/superio/smsc/smscsuperio/superio.c
+++ b/src/superio/smsc/smscsuperio/superio.c
@@ -51,6 +51,7 @@
 #define FDC37M81X	0x4d
 #define FDC37M60X	0x47
 #define LPC47B27X	0x51	/* a.k.a. LPC47B272 */
+#define LPC47U33X	0x54
 #define LPC47M10X	0x59	/* Same ID: LPC47M112, LPC47M13X */
 #define LPC47M15X	0x60	/* Same ID: LPC47M192 */
 #define LPC47S45X	0x62
@@ -129,6 +130,7 @@ static const struct logical_devices {
 	{LPC47M15X,{0, 3, 4,  5, -1,  7, -1,  -1, -1,   9, 10, 11, -1, -1, -1}},
 	{LPC47S45X,{0, 3, 4,  5,  6,  7, -1,   8, -1,  -1, -1, -1, 10, -1, 11}},
 	{LPC47B397,{0, 3, 4,  5, -1,  7, -1,  -1,  8,  -1, -1, -1, 10, -1, -1}},
+	{LPC47U33X,{0, 3, 4, -1, -1,  7, -1,  -1, -1,   9,  0,  5, 10,  0, 11}},
 	{A8000,    {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 	{DME1737,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},
 	{SCH3112,  {0, 3, 4,  5, -1,  7, -1,  -1, -1,  -1, -1, -1, 10, -1, -1}},