diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2019-03-06 14:45:12 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-19 21:37:37 +0000 |
| commit | b55cd54d1bc937880bf9aac7093e36a6b2c71d3e (patch) | |
| tree | 6d4853d5dbf725b506f287d14954ded9de4616b6 /src | |
| parent | 1217af5e1a83501b4518f29c7f472453681f704d (diff) | |
soc/intel/braswell: Use IRQ 9 for SCI
Default reserved value of used for SCI IRQ.
Configure SCIS field to use IRQ 9.
BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I09aca433528b6f64ad3ff3753ae8392c0d89cdc0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/braswell/southcluster.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index b8263db6b7..e79cb128a5 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -4,7 +4,7 @@ * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -267,6 +267,7 @@ static void sc_init(struct device *dev) int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const unsigned long ilb_base = ILB_BASE_ADDRESS; void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = dev->chip_info; @@ -274,6 +275,14 @@ static void sc_init(struct device *dev) printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + + /* Use IRQ9 for SCI Interrupt */ + write32((void *)(ilb_base + ACTL), 0); + isa_dma_init(); /* Set up the PIRQ PIC routing based on static config. */ |