sb/intel/bd82x6x/pch.c: Extract common functions

PCH identification functions and `pch_iobp_update` are used in multiple
stages. Move them out of `pch.c` to drop some ugly preprocessor usage.
Subsequent commits will use `pch_iobp_update` in romstage as well.

Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79624
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 123 insertions, 119 deletions

diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 0a4cc8333b..32fddc4742 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -7,6 +7,7 @@ bootblock-y += early_pch.c
 
 ramstage-y += pch.c
 ramstage-y += azalia.c
+ramstage-y += common.c
 ramstage-y += fadt.c
 ramstage-y += lpc.c
 ramstage-y += pci.c
@@ -24,8 +25,9 @@ ramstage-y += me_status.c
 
 ramstage-$(CONFIG_ELOG) += elog.c
 
-smm-y += smihandler.c me_smm.c pch.c me_common.c
+smm-y += common.c smihandler.c me_smm.c me_common.c
 
+romstage-y += common.c
 romstage-y += me_status.c
 romstage-y += early_rcba.c
 romstage-y += early_pch.c
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c
new file mode 100644
index 0000000000..f4c757a060
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/common.c
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define __SIMPLE_DEVICE__
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <stdint.h>
+
+#include "pch.h"
+
+int pch_silicon_revision(void)
+{
+	static int pch_revision_id = -1;
+
+	if (pch_revision_id < 0)
+		pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
+
+	return pch_revision_id;
+}
+
+int pch_silicon_type(void)
+{
+	static int pch_type = -1;
+
+	if (pch_type < 0)
+		pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
+
+	return pch_type;
+}
+
+int pch_silicon_supported(int type, int rev)
+{
+	int cur_type = pch_silicon_type();
+	int cur_rev = pch_silicon_revision();
+
+	switch (type) {
+	case PCH_TYPE_CPT:
+		/* CougarPoint minimum revision */
+		if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
+			return 1;
+		/* PantherPoint any revision */
+		if (cur_type == PCH_TYPE_PPT)
+			return 1;
+		break;
+
+	case PCH_TYPE_PPT:
+		/* PantherPoint minimum revision */
+		if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
+			return 1;
+		break;
+	}
+
+	return 0;
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+	unsigned int try = IOBP_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = RCBA32(IOBPS);
+		if ((data & 1) == 0)
+			return 1;
+		udelay(10);
+	}
+
+	printk(BIOS_ERR, "IOBP timeout\n");
+	return 0;
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+	u32 data;
+
+	/* Set the address */
+	RCBA32(IOBPIRI) = address;
+
+	/* READ OPCODE */
+	if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+		RCBA32(IOBPS) = IOBPS_RW_BX;
+	else
+		RCBA32(IOBPS) = IOBPS_READ_AX;
+	if (!iobp_poll())
+		return;
+
+	/* Read IOBP data */
+	data = RCBA32(IOBPD);
+	if (!iobp_poll())
+		return;
+
+	/* Check for successful transaction */
+	if ((RCBA32(IOBPS) & 0x6) != 0) {
+		printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
+		return;
+	}
+
+	/* Update the data */
+	data &= andvalue;
+	data |= orvalue;
+
+	/* WRITE OPCODE */
+	if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
+		RCBA32(IOBPS) = IOBPS_RW_BX;
+	else
+		RCBA32(IOBPS) = IOBPS_WRITE_AX;
+	if (!iobp_poll())
+		return;
+
+	/* Write IOBP data */
+	RCBA32(IOBPD) = data;
+	if (!iobp_poll())
+		return;
+}
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index a7ab83a24b..32ed5cd4a9 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -11,123 +11,6 @@
 #include "chip.h"
 #include "pch.h"
 
-int pch_silicon_revision(void)
-{
-	static int pch_revision_id = -1;
-
-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-#else
-	struct device *dev = pcidev_on_root(0x1f, 0);
-#endif
-
-	if (pch_revision_id < 0)
-		pch_revision_id = pci_read_config8(dev,	PCI_REVISION_ID);
-	return pch_revision_id;
-}
-
-int pch_silicon_type(void)
-{
-	static int pch_type = -1;
-
-#ifdef __SIMPLE_DEVICE__
-	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-#else
-	struct device *dev = pcidev_on_root(0x1f, 0);
-#endif
-
-	if (pch_type < 0)
-		pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
-	return pch_type;
-}
-
-static int pch_silicon_supported(int type, int rev)
-{
-	int cur_type = pch_silicon_type();
-	int cur_rev = pch_silicon_revision();
-
-	switch (type) {
-	case PCH_TYPE_CPT:
-		/* CougarPoint minimum revision */
-		if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
-			return 1;
-		/* PantherPoint any revision */
-		if (cur_type == PCH_TYPE_PPT)
-			return 1;
-		break;
-
-	case PCH_TYPE_PPT:
-		/* PantherPoint minimum revision */
-		if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
-			return 1;
-		break;
-	}
-
-	return 0;
-}
-
-#define IOBP_RETRY 1000
-static inline int iobp_poll(void)
-{
-	unsigned int try = IOBP_RETRY;
-	u32 data;
-
-	while (try--) {
-		data = RCBA32(IOBPS);
-		if ((data & 1) == 0)
-			return 1;
-		udelay(10);
-	}
-
-	printk(BIOS_ERR, "IOBP timeout\n");
-	return 0;
-}
-
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
-{
-	u32 data;
-
-	/* Set the address */
-	RCBA32(IOBPIRI) = address;
-
-	/* READ OPCODE */
-	if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
-		RCBA32(IOBPS) = IOBPS_RW_BX;
-	else
-		RCBA32(IOBPS) = IOBPS_READ_AX;
-	if (!iobp_poll())
-		return;
-
-	/* Read IOBP data */
-	data = RCBA32(IOBPD);
-	if (!iobp_poll())
-		return;
-
-	/* Check for successful transaction */
-	if ((RCBA32(IOBPS) & 0x6) != 0) {
-		printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
-		return;
-	}
-
-	/* Update the data */
-	data &= andvalue;
-	data |= orvalue;
-
-	/* WRITE OPCODE */
-	if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
-		RCBA32(IOBPS) = IOBPS_RW_BX;
-	else
-		RCBA32(IOBPS) = IOBPS_WRITE_AX;
-	if (!iobp_poll())
-		return;
-
-	/* Write IOBP data */
-	RCBA32(IOBPD) = data;
-	if (!iobp_poll())
-		return;
-}
-
-#ifndef __SIMPLE_DEVICE__
 /* Set bit in function disable register to hide this device */
 static void pch_hide_devfn(unsigned int devfn)
 {
@@ -478,4 +361,3 @@ struct chip_operations southbridge_intel_bd82x6x_ops = {
 	CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge")
 	.enable_dev = pch_enable,
 };
-#endif
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 6d164ead42..3bb8701e5c 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -34,6 +34,7 @@
 
 int pch_silicon_revision(void);
 int pch_silicon_type(void);
+int pch_silicon_supported(int type, int rev);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
 
 void enable_usb_bar(void);