diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-01-08 21:17:18 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:53:17 +0000 |
| commit | b43d74a79827d696866f72da51944a83b5635580 (patch) | |
| tree | 9a4143219d8bd6c9a6b56e9671058f72cbc783b1 /src | |
| parent | 9e71fdd506752391b36c518b545cf03f37351ed5 (diff) | |
mb/intel/jasperlake_rvp: Update FMAP for jslrvp
Remove unused SMM_STORE space and use it for RW_LEGACY area
BUG=None
TEST=None
Change-Id: I5724b860271025e8cb8b320ecbd33352ef779660
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/chromeos.fmd | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index f4db8b4bc7..827e4484ca 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,10 +1,10 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x3F0000 { + SI_ALL@0x0 0x600000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x36F000 + SI_ME@0x81000 0x57F000 } - SI_BIOS@0x400000 0xC00000 { + SI_BIOS@0x600000 0xA00000 { RW_SECTION_A@0x0 0x2d0000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x2bffc0 @@ -28,16 +28,15 @@ FLASH@0xff000000 0x1000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - SMMSTORE(PRESERVE)@0x5d0000 0x40000 - RW_LEGACY(CBFS)@0x610000 0x1c0000 - WP_RO@0x7d0000 0x430000 { + RW_LEGACY(CBFS)@0x5d0000 0x100000 + WP_RO@0x6d0000 0x330000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x42c000 { + RO_SECTION@0x4000 0x32c000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x33c000 + COREBOOT(CBFS)@0xf0000 0x23c000 } } } |