diff options
| author | Kevin Chiu <kevin.chiu.17802@gmail.com> | 2022-12-01 19:25:34 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-07 16:02:56 +0000 |
| commit | b2a6151299b3891f3c7e6e17368bbe552dbdb72a (patch) | |
| tree | 7bd50ce10029b6c9a9044c26829c5d6793049b1b /src | |
| parent | 4862d53ff25a5dc1c4e15a87240c666fa9bc2c6c (diff) | |
mb/google/brya/var/lisbon: Update fw_config STORAGE field
option STORAGE_EMMC 0
option STORAGE_NVME 1
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Idd52112743ee0d64aca630e54511503607770d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/lisbon/overridetree.cb | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 6c471b3245..7524b6783e 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -1,7 +1,7 @@ fw_config - field AUDIO 0 2 - option AUDIO_UNKNOWN 0 - option ALC5682IVS_I2S 1 + field STORAGE 1 1 + option STORAGE_EMMC 0 + option STORAGE_NVME 1 end end @@ -149,7 +149,8 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" - end + probe STORAGE STORAGE_NVME + end #NVMe device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp2 off end @@ -173,9 +174,7 @@ chip soc/intel/alderlake register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" - device i2c 1a on - probe AUDIO ALC5682IVS_I2S - end + device i2c 1a on end end end #I2C0 device ref i2c1 on @@ -211,6 +210,7 @@ chip soc/intel/alderlake .clk_req = 4, .flags = PCIE_RP_HOTPLUG | PCIE_RP_AER, }" + probe STORAGE STORAGE_EMMC end #PCIE12 EMMC device ref gspi1 off end device ref pch_espi on |