diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-05 10:11:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-11 16:44:50 +0000 |
| commit | b045135524edc681dae151a5a477b2514c7199b8 (patch) | |
| tree | 2a627b792f44fa92e5745b442720d6f6d4f6606a /src | |
| parent | a44affd550b6ab8d64a50e4e3a72408b2061d2d9 (diff) | |
mb/siemens/mc_ehl1: Use SSD type for SATA ports
There are only SSD connected to SATA ports on this mainboard. To prevent
misbehavior, set the correct hard drive type for enabled SATA ports.
BUG=none
TEST=Boot into OS and check the stability of the SSD
Change-Id: I116b1e36f0582956604c3c2508961ffb3de0898a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74947
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 4e2fffc544..107ff72a96 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -80,6 +80,8 @@ chip soc/intel/elkhartlake register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" + register "SataPortsSSD[0]" = "1" + register "SataPortsSSD[1]" = "1" register "SataSpeed" = "SATA_GEN2" register "ScsEmmcHs400Enabled" = "0" |