diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2023-08-13 12:52:14 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-08-15 03:19:32 +0000 |
| commit | af1534f5afb6f3c64e24052a77a3bbbc8455b94c (patch) | |
| tree | e55e2db24c12a506b7611ad2f9be1b2d52dcd6a8 /src | |
| parent | 108b99bab861136af9a5f0771e7ed118aef4cbaa (diff) | |
soc/nvidia/tegra210/mipi-phy: Remove space before semicolon
Change-Id: I107e2952bcca864a1cacf240cca301011df44719
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/nvidia/tegra210/mipi-phy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 4592e6a931..48a908a7d3 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -26,7 +26,7 @@ int mipi_dphy_set_timing(struct tegra_dsi *dsi) u32 tclkpost = ((DSI_PHY_TIMING_DIV(((70) + ((52) * (DSI_TBIT(freq)))), freq))); u32 tclkzero = (DSI_PHY_TIMING_DIV(260, freq)); - u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq)) ; + u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq)); u32 tclkprepare = (DSI_PHY_TIMING_DIV(60, freq)); u32 tclkpre = 1; //min = 8*UI per mipi spec, tclk_pre=0 should be ok, but using 1 value u32 twakeup = 0x7F; //min = 1ms |