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authorJamie Chen <jamie.chen@intel.com>2021-06-03 11:10:57 +0800
committerNick Vaccaro <nvaccaro@google.com>2021-08-12 18:00:54 +0000
commitadda399234603c38b983331a8deeebc070fb82aa (patch)
tree86d8071b83b373f27c1de4d96ff065bfa77581de /src
parent9f7e9cbc2686c478af3d9cd17ea3103cf9fb1d20 (diff)
soc/intel/apollolake: change LPDDR4 density enum definition
Originally we use rank_density=0 to mean disable the channel, but actually rank_density=0 means 4Gb density in the FSP. This patch changes the LPDDR4 enum values to the real density number and adds a switch statement to mapping the density define in the FSP. BUG=b:178665760 BRANCH=NONE TEST=build fw and flash to the dut, the dut can boot up successfully. Change-Id: I36dba2cef130211e7aea9e2a4f82c5db78f82a83 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56805 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/include/soc/meminit.h8
-rw-r--r--src/soc/intel/apollolake/meminit.c48
2 files changed, 25 insertions, 31 deletions
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index 83cf809453..b08427026f 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -51,9 +51,9 @@ enum {
/* LPDDR4 module density in bits. */
enum {
- LP4_8Gb_DENSITY = 2,
- LP4_12Gb_DENSITY,
- LP4_16Gb_DENSITY,
+ LP4_8Gb_DENSITY = 8,
+ LP4_12Gb_DENSITY = 12,
+ LP4_16Gb_DENSITY = 16,
};
/*
@@ -93,7 +93,7 @@ void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed);
* to the memory reference code.
*/
void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
- int rank_density, int dual_rank,
+ int rank_density_gb, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg);
struct lpddr4_sku {
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 86015715bc..d744ac6a87 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -19,24 +19,7 @@ static void accumulate_channel_memory(int density, int dual_rank)
/* For this platform LPDDR4 memory is 4 DRAM parts that are x32. 2 of
the parts are composed into a x64 memory channel. Thus there are 2
channels composed of 2 DRAMs. */
- size_t sz;
-
- /* Per rank density in Gb */
- switch (density) {
- case LP4_8Gb_DENSITY:
- sz = 8;
- break;
- case LP4_12Gb_DENSITY:
- sz = 12;
- break;
- case LP4_16Gb_DENSITY:
- sz = 16;
- break;
- default:
- printk(BIOS_ERR, "Invalid DRAM density: %d\n", density);
- sz = 0;
- break;
- }
+ size_t sz = density;
/* Two DRAMs per channel. */
sz *= 2;
@@ -289,27 +272,38 @@ static void enable_logical_chan1(FSP_M_CONFIG *cfg,
}
void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
- int rank_density, int dual_rank,
+ int rank_density_gb, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg)
{
- if (rank_density < LP4_8Gb_DENSITY ||
- rank_density > LP4_16Gb_DENSITY) {
- printk(BIOS_ERR, "Invalid LPDDR4 density: %d\n", rank_density);
+ int fsp_rank_density;
+
+ switch (rank_density_gb) {
+ case LP4_8Gb_DENSITY:
+ fsp_rank_density = 2;
+ break;
+ case LP4_12Gb_DENSITY:
+ fsp_rank_density = 3;
+ break;
+ case LP4_16Gb_DENSITY:
+ fsp_rank_density = 4;
+ break;
+ default:
+ printk(BIOS_ERR, "Invalid LPDDR4 density: %d Gb\n", rank_density_gb);
return;
}
switch (logical_chan) {
case LP4_LCH0:
- enable_logical_chan0(cfg, rank_density, dual_rank, scfg);
+ enable_logical_chan0(cfg, fsp_rank_density, dual_rank, scfg);
break;
case LP4_LCH1:
- enable_logical_chan1(cfg, rank_density, dual_rank, scfg);
+ enable_logical_chan1(cfg, fsp_rank_density, dual_rank, scfg);
break;
default:
printk(BIOS_ERR, "Invalid logical channel: %d\n", logical_chan);
return;
}
- accumulate_channel_memory(rank_density, dual_rank);
+ accumulate_channel_memory(rank_density_gb, dual_rank);
}
void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
@@ -330,7 +324,7 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
meminit_lpddr4(cfg, sku->speed);
if (sku->ch0_rank_density) {
- printk(BIOS_INFO, "LPDDR4 Ch0 density = %d\n",
+ printk(BIOS_INFO, "LPDDR4 Ch0 density = %d Gb\n",
sku->ch0_rank_density);
meminit_lpddr4_enable_channel(cfg, LP4_LCH0,
sku->ch0_rank_density,
@@ -339,7 +333,7 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
}
if (sku->ch1_rank_density) {
- printk(BIOS_INFO, "LPDDR4 Ch1 density = %d\n",
+ printk(BIOS_INFO, "LPDDR4 Ch1 density = %d Gb\n",
sku->ch1_rank_density);
meminit_lpddr4_enable_channel(cfg, LP4_LCH1,
sku->ch1_rank_density,