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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-12-08 03:00:26 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-12-09 09:03:22 +0100 |
| commit | a9a2e10eed693f1e0e60ea72c269125d3fadcb8a (patch) | |
| tree | 1d969def8ae866c248921e1381c140dd74097148 /src | |
| parent | b3b79afd551ce513e98b8719294bc356ceb4f781 (diff) | |
southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop
Correct mask to select bits 4-6 inclusively as per comment and use
bitwise operations while working with bits. Be sure to write back out
the data on the retrain.
See:
commit cab9efb2 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop
Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7692
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/amd/sr5650/sr5650.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 7fdecf1dae..2a2d558a70 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -238,13 +238,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); - tmp = (reg >> 4) && 0x3; /* get bit4-6 */ + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); + tmp = (reg >> 4) & 0x7; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ reg |= 1 << 8; + nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg); count++; /* CIM said "keep in loop"? */ } else { res = 1; |