diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-12-10 18:38:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-15 22:38:04 +0000 |
| commit | a3930dafd42e10f2003148b0acf8cb28265eaba0 (patch) | |
| tree | b7b083937e23b076b9d2aa0983a4ce5eefcfd23b /src | |
| parent | 6b0f45199c5cbbcabc94b98968d34d0f1f98df35 (diff) | |
soc/amd/common/block/spi/fch_spi_ctrl: rework dump_state
Introduce and use enum spi_dump_state_phase to indicate from which phase
of the SPI transfer dump_state gets called to print the relevant debug
information for that phase.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi_ctrl.c | 31 |
1 files changed, 25 insertions, 6 deletions
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index d95b64275b..aad8de7f69 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -30,7 +30,12 @@ #define SPI_FIFO_RD_PTR_SHIFT 16 #define SPI_FIFO_RD_PTR_MASK 0x7f -static void dump_state(const char *str, u8 phase) +enum spi_dump_state_phase { + SPI_DUMP_STATE_BEFORE_CMD, + SPI_DUMP_STATE_AFTER_CMD, +}; + +static void dump_state(enum spi_dump_state_phase phase) { u8 dump_size; u32 addr; @@ -38,19 +43,33 @@ static void dump_state(const char *str, u8 phase) if (!CONFIG(SOC_AMD_COMMON_BLOCK_SPI_DEBUG)) return; - printk(BIOS_DEBUG, "SPI: %s\n", str); + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: + printk(BIOS_DEBUG, "SPI: Before execute\n"); + break; + case SPI_DUMP_STATE_AFTER_CMD: + printk(BIOS_DEBUG, "SPI: Transaction finished\n"); + break; + default: /* We shouldn't reach this */ + return; + } + printk(BIOS_DEBUG, "Cntrl0: %x\n", spi_read32(SPI_CNTRL0)); printk(BIOS_DEBUG, "Status: %x\n", spi_read32(SPI_STATUS)); addr = spi_get_bar() + SPI_FIFO; - if (phase == 0) { + + switch (phase) { + case SPI_DUMP_STATE_BEFORE_CMD: dump_size = spi_read8(SPI_TX_BYTE_COUNT); printk(BIOS_DEBUG, "TxByteCount: %x\n", dump_size); printk(BIOS_DEBUG, "CmdCode: %x\n", spi_read8(SPI_CMD_CODE)); - } else { + break; + case SPI_DUMP_STATE_AFTER_CMD: dump_size = spi_read8(SPI_RX_BYTE_COUNT); printk(BIOS_DEBUG, "RxByteCount: %x\n", dump_size); addr += spi_read8(SPI_TX_BYTE_COUNT); + break; } if (dump_size > 0) @@ -74,7 +93,7 @@ static int wait_for_ready(void) static int execute_command(void) { - dump_state("Before execute", 0); + dump_state(SPI_DUMP_STATE_BEFORE_CMD); spi_write8(SPI_CMD_TRIGGER, SPI_CMD_TRIGGER_EXECUTE); @@ -82,7 +101,7 @@ static int execute_command(void) printk(BIOS_ERR, "FCH_SC Error: Timeout executing command\n"); - dump_state("Transaction finished", 1); + dump_state(SPI_DUMP_STATE_AFTER_CMD); return 0; } |