diff options
| author | Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> | 2024-02-08 10:01:35 +0900 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-21 13:48:05 +0000 |
| commit | a2f47bbd93117063130b3bd595bcfcde66ef53b2 (patch) | |
| tree | 8d80cdcbbc9e31358830e4c755051383b13d241e /src | |
| parent | c6df1ac62c4cfd3284e4a454ffa53989c8f7ff6e (diff) | |
mb/google/brya/var/xol: Update thermal policy
Update initial DTT policy and TCC setting for Xol. The setting values
are from internal power team.
- Critical CPU temparature: 105 -> 99
- TCC offset: 90 -> 94
BUG=b:323989520
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I546b313a1e6af16029309174a5bed2d1e4aa4d11
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80410
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/xol/overridetree.cb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 205b43f54f..8ace1e7637 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -12,6 +12,8 @@ chip soc/intel/alderlake # display flickering issue. register "disable_dynamic_tccold_handshake" = "true" + register "tcc_offset" = "6" # TCC of 94 + register "platform_pmax" = "145" register "usb2_ports[0]" = "{ @@ -200,7 +202,7 @@ chip soc/intel/alderlake ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 99, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), |