diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2019-02-27 11:20:24 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-29 06:36:39 +0000 |
| commit | 9f1162949544e9becf8b68ebb95c4609c199a9d7 (patch) | |
| tree | 62cbd2b4737f2eb910ce3c331d1327f7491d6ff5 /src | |
| parent | e447aec904c3a8b5aa9cc2ed2cec48c449604d91 (diff) | |
mb/google/hatch: Deassert EN_PP3300_WWAN during sleep
Deassert EN_PP3300_WWAN to turn the WWAN module completely off when
entering S5. This is the same fix in commit eeb475c5c for coral board.
BUG=none
BRANCH=none
TEST=On hatch, Perform a quick system power cycle, verify that the modem
is powered cycle and the SIM with PIN lock enabled requests unlocking.
Change-Id: I3ec8ccb7618189b9e8586f5571a68d3309597ee7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
4 files changed, 36 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c index af069e11ad..68d562dd0f 100644 --- a/src/mainboard/google/hatch/smihandler.c +++ b/src/mainboard/google/hatch/smihandler.c @@ -12,7 +12,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <baseboard/variants.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> @@ -27,6 +27,12 @@ void mainboard_smi_espi_handler(void) void mainboard_smi_sleep(u8 slp_typ) { + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(slp_typ, &num); + gpio_configure_pads(pads, num); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc index 3c12e14a0a..5d5695fe5f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc @@ -21,3 +21,5 @@ romstage-y += memory.c ramstage-y += gpio.c verstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 68bbaabee1..b974e49ee8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -411,6 +411,30 @@ const struct pad_config *__weak variant_gpio_table(size_t *num) return gpio_table; } +/* Default GPIO settings before entering sleep. */ +static const struct pad_config default_sleep_gpio_table[] = { +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, + * turn off EN_PP3300_WWAN. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ +}; + +const struct pad_config * __weak +variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} + /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { /* B15 : H1_SLAVE_SPI_CS_L */ diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h index aa7c67d693..fd39c4516f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h @@ -32,6 +32,9 @@ int variant_memory_sku(void); /* Return board specific memory configuration */ void variant_memory_params(struct cnl_mb_cfg *bcfg); +/* Return variant specific gpio pads to be configured during sleep */ +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); + /* Return ChromeOS gpio table and fill in number of entries. */ const struct cros_gpio *variant_cros_gpios(size_t *num); |