sb/intel/i82801ix: Add common code to set up LPC IO decode ranges

This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
  decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
  somehow a board needs to override this behavior it can happen in the
  mb_setup_superio() hook (that will be renamed when moving to
  C_ENVIRONMENT_BOOTBLOCK).

Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

11 files changed, 48 insertions, 55 deletions

diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index b4c2ea89b1..9561dfa93f 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -75,6 +75,9 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
 
 			device pci 19.0 on end # LAN
 			device pci 1a.0 on # UHCI
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 1b763188e8..e8215654e1 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -14,16 +14,12 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
 #include <console/console.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <southbridge/intel/common/gpio.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include "dock.h"
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-
 static void hybrid_graphics_init(sysinfo_t *sysinfo)
 {
 	bool peg, igd;
@@ -36,20 +32,6 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
 
 static int dock_err;
 
-void mb_setup_lpc(void)
-{
-	/* Set up SuperIO LPC forwards */
-
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
-	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
-}
-
 void mb_setup_superio(void)
 {
 	/* Minimal setup to detect dock */
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 2ed4308cfa..4efcc255ec 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -79,6 +79,9 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
 
 			device pci 19.0 on end # LAN
 			device pci 1a.0 on # UHCI
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 4382bc084d..41be94f357 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -14,25 +14,9 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
 #include <southbridge/intel/common/gpio.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-
-void mb_setup_lpc(void)
-{
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
-	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
-}
-
 void get_mb_spd_addrmap(u8 *spd_addrmap)
 {
 	spd_addrmap[0] = 0x50;
diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb
index 4300171207..ddb2ad72a9 100644
--- a/src/mainboard/roda/rk9/devicetree.cb
+++ b/src/mainboard/roda/rk9/devicetree.cb
@@ -67,6 +67,8 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }"
 
+			register "gen1_dec" = "0x000c0601"
+
 			device pci 19.0 off end # LAN
 			device pci 1a.0 on # UHCI
 				ioapic_irq 2 INTA 0x10
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 497828b58a..b37b5c5f63 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -16,27 +16,11 @@
 
 #include <arch/io.h>
 #include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <southbridge/intel/common/gpio.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <superio/smsc/lpc47n227/lpc47n227.h>
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
 
-void mb_setup_lpc(void)
-{
-	/* Set up SuperIO LPC forwards */
-
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	/* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
-}
-
 void mb_setup_superio(void)
 {
 	/* Original settings:
@@ -71,9 +55,6 @@ void mb_setup_superio(void)
 	/* Exit configuration state. */
 	pnp_exit_conf_state(sio);
 
-	/* Enable decoding of 0x600-0x60f through lpc. */
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
-
 	/* Set GPIO output values: */
 	outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
 	outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 430afe4077..5c28f533a9 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -435,7 +435,6 @@ u32 decode_tseg_size(u8 esmramc);
 void init_iommu(void);
 
 /* romstage mainboard hookups */
-void mb_setup_lpc(void);
 void mb_setup_superio(void); /* optional */
 void get_mb_spd_addrmap(u8 spd_addrmap[4]);
 void mb_pre_raminit_setup(sysinfo_t *); /* optional */
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index c853a3a1f4..7f45ca7f83 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -62,7 +62,7 @@ void mainboard_romstage_entry(void)
 	i82801ix_early_init();
 	setup_pch_gpios(&mainboard_gpio_map);
 
-	mb_setup_lpc();
+	i82801ix_lpc_decode();
 
 	mb_setup_superio();
 
diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h
index 0b3e0b5a50..73ee822f74 100644
--- a/src/southbridge/intel/i82801ix/chip.h
+++ b/src/southbridge/intel/i82801ix/chip.h
@@ -88,6 +88,12 @@ struct southbridge_intel_i82801ix_config {
 	} pcie_power_limits[6];
 
 	uint8_t pcie_hotplug_map[8];
+
+	/* Additional LPC IO decode ranges */
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
+	uint32_t gen3_dec;
+	uint32_t gen4_dec;
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index da124ff54f..51ce9e859e 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -17,6 +17,7 @@
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include "i82801ix.h"
+#include "chip.h"
 
 void i82801ix_early_init(void)
 {
@@ -58,3 +59,34 @@ void i82801ix_early_init(void)
 	/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
 	         before they get cleared. */
 }
+
+void i82801ix_lpc_decode(void)
+{
+	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
+	const struct device *dev = pcidev_on_root(0x1f, 0);
+	const struct southbridge_intel_i82801ix_config *config = NULL;
+
+	/* Configure serial IRQs.*/
+	pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
+	/*
+	 * Enable some common LPC IO ranges:
+	 * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
+	 * - 0x60/0x64, 0x62/0x66 often KBC/EC
+	 * - 0x3f0-0x3f5/0x3f7 FDD
+	 * - 0x378-0x37f and 0x778-0x77f LPT
+	 * - 0x2f8-0x2ff COMB
+	 * - 0x3f8-0x3ff COMA
+	 */
+	pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
+	pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f);
+
+	/* Set up generic decode ranges */
+	if (!dev || !dev->chip_info)
+		return;
+	config = dev->chip_info;
+
+	pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
+	pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
+	pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
+	pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
+}
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index afaaade82d..7c4faf0142 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -210,6 +210,7 @@ void aseg_smm_lock(void);
 
 void enable_smbus(void);
 void i82801ix_early_init(void);
+void i82801ix_lpc_decode(void);
 void i82801ix_dmi_setup(void);
 void i82801ix_dmi_poll_vc1(void);