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authorSean Rhodes <sean@starlabs.systems>2022-05-26 22:20:41 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-06-20 12:07:52 +0000
commit9d894b856361f6f8978d6c27557f8dd0bd84d2df (patch)
tree63bfee38338730e238f64b1b01526a9b8fc52cee /src
parent9088b681f539873e70a8904ca41165f3e830232f (diff)
soc/intel/apollolake: Hook up C1e to enhanced_cstates
Hook up C1e FSP S UPD which enables enhanced C-states, to enhanced_cstates. This allows it to be enabled in the devicetree with a value of "1" as the default is disabled. C1e exists on both APL and GLK, and has been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/chip.c3
-rw-r--r--src/soc/intel/apollolake/chip.h3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 20bbde9288..e824328350 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -717,6 +717,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->VmxEnable = CONFIG(ENABLE_VMX);
+ /* Enable enhanced C-states */
+ silconfig->C1e = cfg->enhanced_cstates;
+
/* Set VTD feature according to devicetree */
silconfig->VtdEnable = get_uint_option("vtd", cfg->enable_vtd);
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 209937d775..de3ba9780c 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -135,6 +135,9 @@ struct soc_intel_apollolake_config {
uint8_t hdaudio_pwr_gate_enable;
uint8_t hdaudio_bios_config_lockdown;
+ /* Enhanced C-states */
+ int enhanced_cstates;
+
/* SLP S3 minimum assertion width. */
int slp_s3_assertion_width_usecs;