diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-23 12:20:46 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-25 04:22:42 +0000 |
| commit | 9bf9adae13b01cb400975d4d409bb3eb484c8a63 (patch) | |
| tree | a8b878b36ef17d8c6e56b37ff205ad6c927c46c3 /src | |
| parent | 7ff3f31cd17a08a5052b29879c50287d76a1f094 (diff) | |
soc/intel/skylake: Use `devfn_disable()` to handle XDCI
Done for consistency with other Intel SoCs. This allows moving the
pattern inside a helper function.
Change-Id: If95c4b6c1602e56436150a931210692f14630694
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55787
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f0ed699b90..865fdf0f78 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -226,7 +226,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_CONFIG *params = &supd->FspsConfig; FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct soc_intel_skylake_config *config; - struct device *dev; uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; @@ -458,14 +457,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->ShowSpiController = is_devfn_enabled(PCH_DEVFN_SPI); /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (dev) { - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; - } else { - params->XdciEnable = 0; - } + if (!xdci_can_enable()) + devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG); + params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG); /* Enable or disable Gaussian Mixture Model in devicetree */ params->GmmEnable = is_devfn_enabled(SA_DEVFN_GMM); |