diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-04-18 23:49:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-22 05:37:57 +0000 |
| commit | 9bb269060954e740fd117036281072288814e302 (patch) | |
| tree | 0ae878466cabacd86598db53daa464afeac093c6 /src | |
| parent | 3879334ca0d73c84a03416a73fcf52c95f39ba6b (diff) | |
soc/intel/alderlake: Implement `soc_is_ish_partition_enabled` override
This patch implements `soc_is_ish_partition_enabled()` override to
uniquely identify the SKU type between UFS and non-UFS to conclude
if ISH partition is enabled and need to retrieve the ISH version from
CSE FPT by sending HECI command.
TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting
to google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74532
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 7cdeb7cc9a..f052279880 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -162,6 +162,26 @@ const char *soc_acpi_name(const struct device *dev) } #endif +#if CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) +/* + * SoC override API to identify if ISH Firmware existed inside CSE FPT. + * + * SoC with UFS enabled would like to keep ISH enabled as well, hence + * identifying the UFS enabled device is enough to conclude that the ISH + * partition also is available. + */ +bool soc_is_ish_partition_enabled(void) +{ + struct device *ufs = pcidev_path_on_root(PCH_DEVFN_UFS); + uint16_t ufs_pci_id = ufs ? pci_read_config16(ufs, PCI_DEVICE_ID) : 0xFFFF; + + if (ufs_pci_id == 0xFFFF) + return false; + + return true; +} +#endif + /* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */ static void soc_fill_gpio_pm_configuration(void) { |