soc/intel/cannonlake: Program DMI PCR settings

According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs
to be programmed before it gets locked. Update lpc programming to add
decode programming on DMI side as well. Also enabled io port 0x200
decoding by default.

BUG=b.70765863
TEST=Apply changes and add chromeos EC decoding in mainboard
devicetree.cb, then read back IO port in depthcharge cli and check
that return is not zero.

Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 26 insertions, 27 deletions

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index d4ca4072bd..f357a039e0 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -24,6 +24,7 @@ romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
 romstage-y += gpio.c
 romstage-y += gspi.c
 romstage-y += i2c.c
+romstage-y += lpc.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
 romstage-y += reset.c
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index 47eaceb3f9..ae413d5813 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -39,11 +39,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_LPCLGIR1	0x2730
-#define PCR_DMI_LPCLGIR2	0x2734
-#define PCR_DMI_LPCLGIR3	0x2738
-#define PCR_DMI_LPCLGIR4	0x273c
-
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
 #define PCR_DMI_PMBASEA		0x27AC
@@ -176,7 +171,7 @@ void pch_early_iorange_init(void)
 	}
 
 	/* IO Decode Enable */
-	dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN;
+	dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;
 	pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
 	pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
 }
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index e906d9981d..d0253edf30 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -48,6 +48,26 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
 	return cnl_lpc_fixed_mmio_ranges;
 }
 
+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
+{
+	const config_t *config = dev->chip_info;
+
+	gen_io_dec[0] = config->gen1_dec;
+	gen_io_dec[1] = config->gen2_dec;
+	gen_io_dec[2] = config->gen3_dec;
+	gen_io_dec[3] = config->gen4_dec;
+}
+
+void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
+{
+	/* Mirror these same settings in DMI PCR */
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
+}
+
+#if ENV_RAMSTAGE
 static void pch_enable_ioapic(const struct device *dev)
 {
 	u32 reg32;
@@ -70,27 +90,6 @@ static void pch_enable_ioapic(const struct device *dev)
 	 */
 	io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01);
 }
-
-void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
-{
-	const config_t *config = dev->chip_info;
-
-	gen_io_dec[0] = config->gen1_dec;
-	gen_io_dec[1] = config->gen2_dec;
-	gen_io_dec[2] = config->gen3_dec;
-	gen_io_dec[3] = config->gen4_dec;
-}
-
-void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
-{
-	/* Mirror these same settings in DMI PCR */
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
-	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
-}
-
-
 /*
  * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  * 0x00 - 0000 = Reserved
@@ -204,3 +203,4 @@ void lpc_init(struct device *dev)
 	i8259_configure_irq_trigger(9, 1);
 	clock_gate_8254(dev);
 }
+#endif
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 8b3794f4e9..2673f3700b 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <fsp/util.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/pmclib.h>
 #include <memory_info.h>
 #include <soc/iomap.h>
@@ -46,6 +47,8 @@ asmlinkage void car_stage_entry(void)
 	/* initialize Heci interface */
 	heci_init(HECI1_BASE_ADDRESS);
 
+	/* Program LPC generic decoding */
+	pch_enable_lpc();
 	timestamp_add_now(TS_START_ROMSTAGE);
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);