diff options
| author | Victor Ding <victording@google.com> | 2022-11-08 06:53:17 +0000 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-11-10 00:59:48 +0000 |
| commit | 970e33a16811d61162b94b3e7b292d51791ee1f2 (patch) | |
| tree | deb760b4908c0df8ff165c52d710ad17ba9da8aa /src | |
| parent | 48f9b8b773b1b87a69c2f1c6640f173de6e320e1 (diff) | |
mb/google/nissa/var/pujjo: Update register parameters for SX9324 tunning
Update SX9324 related settings based on tunned values from the ODM.
This patch supports both legacy and upstream Linux's SX9324 driver.
BUG=b:242662878
TEST=i2cdump -y -f 13 0x28
(Verified register values on Pujjo)
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I34d8073ffe93e6939f8da0cd7efb8667c0e9ac37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69366
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjo/overridetree.cb | 45 |
1 files changed, 32 insertions, 13 deletions
diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index d7d36e1777..fd022a9074 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -394,19 +394,23 @@ chip soc/intel/alderlake register "reg_afe_ctrl1" = "0x10" register "reg_afe_ctrl2" = "0x00" register "reg_afe_ctrl3" = "0x00" - register "reg_afe_ctrl4" = "0x07" + register "reg_afe_ctrl4" = "0x47" register "reg_afe_ctrl5" = "0x00" register "reg_afe_ctrl6" = "0x00" - register "reg_afe_ctrl7" = "0x07" + register "reg_afe_ctrl7" = "0x47" register "reg_afe_ctrl8" = "0x12" - register "reg_afe_ctrl9" = "0x0f" - register "reg_prox_ctrl0" = "0x12" - register "reg_prox_ctrl1" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0a" + register "reg_prox_ctrl1" = "0x0a" register "reg_prox_ctrl2" = "0x90" register "reg_prox_ctrl3" = "0x60" register "reg_prox_ctrl4" = "0x0c" - register "reg_prox_ctrl5" = "0x12" - register "reg_prox_ctrl6" = "0x3c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x19" register "reg_prox_ctrl7" = "0x58" register "reg_adv_ctrl0" = "0x00" register "reg_adv_ctrl1" = "0x00" @@ -418,17 +422,32 @@ chip soc/intel/alderlake register "reg_adv_ctrl7" = "0x00" register "reg_adv_ctrl8" = "0x00" register "reg_adv_ctrl9" = "0x00" - register "reg_adv_ctrl10" = "0x5c" - register "reg_adv_ctrl11" = "0x52" - register "reg_adv_ctrl12" = "0xb5" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" register "reg_adv_ctrl13" = "0x00" register "reg_adv_ctrl14" = "0x80" register "reg_adv_ctrl15" = "0x0c" - register "reg_adv_ctrl16" = "0x38" + register "reg_adv_ctrl16" = "0x08" register "reg_adv_ctrl17" = "0x56" register "reg_adv_ctrl18" = "0x33" - register "reg_adv_ctrl19" = "0xf0" - register "reg_adv_ctrl20" = "0xf0" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "2" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" device i2c 28 on probe LTE LTE_PRESENT end |