diff options
| author | Jon Murphy <jpmurphy@google.com> | 2022-02-16 06:45:49 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-26 00:15:58 +0000 |
| commit | 960fb2f4b8bcf18c108e6db1a81c2d1584e88126 (patch) | |
| tree | 63340dd5e2cfb0a4cf0b4ddac78d236e20c3d780 /src | |
| parent | 4de2c342fbfe2d96afe1f4d6ccd9be22367aacad (diff) | |
mb/google/skyrim: Enable ACPI tables
Add GPIO initialization and ACPI generation for tables
BUG=b:214415303
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/skyrim/chromeos.c | 14 | ||||
| -rw-r--r-- | src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h | 5 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/skyrim/chromeos.c b/src/mainboard/google/skyrim/chromeos.c new file mode 100644 index 0000000000..a729fce29f --- /dev/null +++ b/src/mainboard/google/skyrim/chromeos.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h index b94afac4bf..dbbb85d19c 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h @@ -3,4 +3,9 @@ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ +#include <soc/gpio.h> + +/* SPI Write protect */ +#define CROS_WP_GPIO GPIO_138 + #endif /* __BASEBOARD_GPIO_H__ */ |