diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-08-11 04:57:32 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-14 14:03:18 +0000 |
| commit | 9419820127398073ab9717057a796cc825eb0eff (patch) | |
| tree | e07f434525a167d33e25a7b9a1eb720544816a88 /src | |
| parent | c4b7fad847f3136bd97d26f02c525deb6cdb79fe (diff) | |
soc/intel/adl,mtl/romstage/fsp_params: fix clock request warning
If a root port doesn't use a clock request pin, we shouldn't check if
this pin number, which defaults to 0 when not set, is already used. This
fixes the following spurious warning that was previously printed for
each external PCIe port which has the 'PCIE_RP_CLK_REQ_UNUSED' flag set
and didn't set 'clk_req' to some unused clock request pin number:
Found overlapped clkreq assignment on clk req 0
Tested on the cw-al-4l-v2.0 mainboard that uses an Alder Lake N100 SoC
which I'm currently porting coreboot to. Also changing this for Meteor
Lake, since they have the same implementation in their romstage
fsp_params.c file
Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 8 |
2 files changed, 10 insertions, 6 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index d917e6cdfe..a63b64c966 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -71,10 +71,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ printk(BIOS_WARNING, "Missing root port clock structure definition\n"); continue; } - if (clk_req_mapping & (1 << cfg[i].clk_req)) - printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" - , cfg[i].clk_req); + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { + if (clk_req_mapping & (1 << cfg[i].clk_req)) + printk(BIOS_WARNING, + "Found overlapped clkreq assignment on clk req %d\n", + cfg[i].clk_req); m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; clk_req_mapping |= 1 << cfg[i].clk_req; } diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 9734c63d5f..055fec7fad 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -52,10 +52,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, printk(BIOS_WARNING, "Missing root port clock structure definition\n"); continue; } - if (clk_req_mapping & (1 << cfg[i].clk_req)) - printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" - , cfg[i].clk_req); + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { + if (clk_req_mapping & (1 << cfg[i].clk_req)) + printk(BIOS_WARNING, + "Found overlapped clkreq assignment on clk req %d\n", + cfg[i].clk_req); m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; clk_req_mapping |= 1 << cfg[i].clk_req; } |