diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-02-20 20:18:43 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-02-25 03:56:59 +0000 |
| commit | 9305ccada13986d21ffaf874507f2d811d1ebe7b (patch) | |
| tree | 0f9bf9d663fbbed1c895d73593d36973196a53c5 /src | |
| parent | 313fdb28ca6b6479c3305d8a385389de0b2290dd (diff) | |
mb/google/rex/var/karis: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Karis has RO locked, any change in the bootblock won't be
applicable for FSI'ed karis devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is
TEST=Able to build and boot google/karis using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.
Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80663
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rex/variants/karis/gpio.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/mainboard/google/rex/variants/karis/gpio.c b/src/mainboard/google/rex/variants/karis/gpio.c index db742d7d1d..1073f06898 100644 --- a/src/mainboard/google/rex/variants/karis/gpio.c +++ b/src/mainboard/google/rex/variants/karis/gpio.c @@ -367,10 +367,8 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* GPP_A19 : [] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_A19, 0, DEEP), /* GPP_A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 1, DEEP), + PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_B16 : [] ==> SOC_HDMI_HPD_L */ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), @@ -405,16 +403,14 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_C00, 1, DEEP), /* GPP_C01 : [] ==> SOC_TCHSCR_RST_R_L */ PAD_CFG_GPO(GPP_C01, 0, DEEP), -}; -static const struct pad_config romstage_gpio_table[] = { /* GPP_A19 : [] ==> EN_PP3300_SSD */ PAD_CFG_GPO(GPP_A19, 1, DEEP), +}; +static const struct pad_config romstage_gpio_table[] = { /* GPP_B11 : [] ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_B11, 0, DEEP), - /* A20 : [] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_A20, 0, DEEP), /* GPP_C23 : [] ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPP_C00 : [] ==> EN_TCHSCR_PWR */ @@ -423,6 +419,8 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_C01, 0, DEEP), /* GPP_D02 : Not Connected */ PAD_NC(GPP_D02, NONE), + /* GPP_A20 : [] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) |