mb/intel/adlrvp: Add new upd setting for ADL RVP with Raptor Lake

Currently, ADL FSP headers and RPL FSP headers differ. Set a RPL only
upd for adlrvp with Raptor Lake silicon. This code can be removed once
ADL and RPL start using the same FSP.

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e69323949233aa8c325a757b28b9d80cbdf4322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

4 files changed, 42 insertions, 0 deletions

diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc
index 0b658e5caa..d37abf561b 100644
--- a/src/mainboard/intel/adlrvp/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/Makefile.inc
@@ -21,6 +21,9 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += romstage_fsp_params.c
 romstage-y += board_id.c
 romstage-y += memory.c
+ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y)
+romstage-y += memory_rpl.c
+endif
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index 4ae10112ce..bb2c3f62b0 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -33,6 +33,7 @@ void variant_configure_early_gpio_pads(void);
 
 size_t variant_memory_sku(void);
 const struct mb_cfg *variant_memory_params(void);
+void rpl_memory_params(FSPM_UPD *memupd);
 
 /* Modify devictree settings during ramstage */
 void variant_devtree_update(void);
diff --git a/src/mainboard/intel/adlrvp/memory_rpl.c b/src/mainboard/intel/adlrvp/memory_rpl.c
new file mode 100644
index 0000000000..a541fbf1e2
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/memory_rpl.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+#include "board_id.h"
+
+void rpl_memory_params(FSPM_UPD *memupd)
+{
+	FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
+
+	int board_id = get_board_id();
+
+	switch (board_id) {
+	case ADL_P_LP4_1:
+	case ADL_P_LP4_2:
+	case ADL_P_DDR4_1:
+	case ADL_P_DDR4_2:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
+		return;
+	case ADL_P_LP5_1:
+	case ADL_P_LP5_2:
+		mem_cfg->Lp5BankMode = 1;
+		return;
+	default:
+	}
+}
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 90d830293f..bf0fb9b124 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -42,6 +42,10 @@ static void configure_external_clksrc(FSP_M_CONFIG *m_cfg)
 		m_cfg->PcieClkSrcUsage[i] = CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER;
 }
 
+__weak void rpl_memory_params(FSPM_UPD *memupd)
+{
+}
+
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
@@ -49,6 +53,12 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 	int board_id = get_board_id();
 
 	/*
+	 * Set Raptor Lake specific new upds that Alder Lake doesn't have.
+	 * This can be removed when Alder Lake and Raptor Lake FSP headers align.
+	 */
+	rpl_memory_params(memupd);
+
+	/*
 	 * Alder Lake common meminit block driver considers bus width to be 128-bit and
 	 * populates the meminit data accordingly. Alder Lake-N has single memory controller
 	 * with 64-bit bus width. By setting half_populated to true, only the bottom half is