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authorAngel Pons <th3fanbus@gmail.com>2020-10-26 00:01:13 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 13:10:05 +0000
commit90f6a31bc2765f989475a30be81b9c075a6fd692 (patch)
tree9b5b3905faffbc9fbe45935fd4df44153462c429 /src
parent79e3a1f8a5c50d27948cb05310989b4e28f3f74c (diff)
nb/intel/haswell/acpi: Move PEG and CTDP includes downwards
This change is just to align with Broadwell. Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46790 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/haswell/acpi/hostbridge.asl12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 3e617ecbb9..35246b3bc6 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -168,12 +168,6 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-/* Configurable TDP */
-#include "ctdp.asl"
-
-/* PCI Express Graphics */
-#include "peg.asl"
-
/* PCI Device Resource Consumption */
Device (PDRC)
{
@@ -202,3 +196,9 @@ Device (PDRC)
Return (PDRS)
}
}
+
+/* Configurable TDP */
+#include "ctdp.asl"
+
+/* PCI Express Graphics */
+#include "peg.asl"