diff options
| author | Shon <shon.wang@quanta.corp-partner.google.com> | 2022-05-24 16:12:11 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-28 04:04:06 +0000 |
| commit | 8f6dd2a4bd8146b9167ec4d2251af1d3045398f2 (patch) | |
| tree | a18d77831caf541a3a002ca8082f60c1796430ec /src | |
| parent | 2bbb6f3064b2af162d53b41b2b4d95581ab5ab9c (diff) | |
mb/google/brya/var/vell: Set empty on USB2_9/USB32_1
The baseboard uses port USB2 #9, and USB3 #1, but vell does not,
therefore set the port configuration to EMPTY.
Change-Id: I0d03b967fd2a051205ad5807f0bd8916bad7c036
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/vell/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index c7f985cde3..23c3e61f14 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -60,6 +60,10 @@ chip soc/intel/alderlake }" register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC3)" # USB2_C3 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" register "sagv" = "SaGv_Enabled" |