diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-06-30 21:00:07 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-04 06:52:07 +0000 |
| commit | 8f23b5d4343c5c8ec1f7f7d453f9d8784fc0d5a2 (patch) | |
| tree | 16f6a9887c64ae65376692e79d03cc668a5a2ca1 /src | |
| parent | 2874330828fa6950bccba04872dbfc8cfae91d99 (diff) | |
drivers/intel/fsp1_1: Adjust postcar MTRRs
Use of romstage_ram_stack_bottom() was invalid, it
potentially uses a different ROMSTAGE_RAM_STACK_SIZE
from the postcar_frame_init() call.
If alignment evaluated to 1 MiB, that WB MTRR may not
have covered all of CBMEM range, having some impact
on boot speeds.
There is no need to accurately describe write-back
MTRR ranges for postcar.
Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/intel/fsp1_1/car.c | 56 |
1 files changed, 7 insertions, 49 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index bd3f4787a0..84ea7d153c 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -14,6 +14,7 @@ */ #include <arch/symbols.h> +#include <cbmem.h> #include <console/console.h> #include <commonlib/helpers.h> #include <cpu/intel/romstage.h> @@ -32,8 +33,7 @@ void platform_enter_postcar(void) { struct postcar_frame pcf; - size_t alignment; - uint32_t aligned_ram; + uintptr_t top_of_ram; if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) die("Unable to initialize postcar frame.\n"); @@ -44,53 +44,11 @@ void platform_enter_postcar(void) /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ - - alignment = mmap_region_granularity(); - aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); - postcar_frame_add_mtrr(&pcf, aligned_ram, alignment, MTRR_TYPE_WRBACK); - - if (CONFIG(HAVE_SMI_HANDLER)) { - void *smm_base; - size_t smm_size; - - /* - * Cache the TSEG region at the top of ram. This region is not - * restricted to SMM mode until SMM has been relocated. By - * setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, (uintptr_t)smm_base, alignment, - MTRR_TYPE_WRBACK); - } + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); run_postcar_phase(&pcf); } |