Add AMD Family 10h PH-E0 support

the patch file comes from
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE
/F10MicrocodePatch010000bf.c

Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/202
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

4 files changed, 169 insertions, 1 deletions

diff --git a/src/cpu/amd/model_10xxx/mc_patch_010000bf.h b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
new file mode 100644
index 0000000000..9baaa9bfdd
--- /dev/null
+++ b/src/cpu/amd/model_10xxx/mc_patch_010000bf.h
@@ -0,0 +1,164 @@
+/*
+ ============================================================
+ Copyright (c) Advanced Micro Devices, Inc., 2004-2008
+
+ The  enclosed microcode  is intended  to be  used  with AMD
+ Microprocessors.  You  may   copy,  view  and  install  the
+ enclosed microcode  only for development  and deployment of
+ firmware,  BIOS,  or  operating  system code  for  computer
+ systems   that  contain  AMD   processors.   You   are  not
+ authorized  to use  the  enclosed microcode  for any  other
+ purpose.
+
+ THE  MICROCODE IS PROVIDED  "AS IS"  WITHOUT ANY  EXPRESS OR
+ IMPLIED WARRANTY  OF ANY KIND, INCLUDING BUT  NOT LIMITED TO
+ WARRANTIES    OF    MERCHANTABILITY,   NON-    INFRINGEMENT,
+ TITLE,FITNESS  FOR  ANY  PARTICULAR PURPOSE,  OR  WARRANTIES
+ ARISING FROM CONDUCT, COURSE  OF DEALING, OR USAGE OF TRADE.
+ AMD does not assume  any responsibility for any errors which
+ may  appear   in  this   microcode  or  any   other  related
+ information provided  to you by  AMD, or result from  use of
+ this microcode.   AMD is not obligated  to furnish, support,
+ or  make   any  further  information,   software,  technical
+ information, know-how, or show-how available related to this
+ microcode.
+
+ The  microcode is provided  with "RESTRICTED  RIGHTS."  Use,
+ duplication, or disclosure by the U.S. Government is subject
+ to  the  restrictions as  set  forth  in  FAR 52.227-14  and
+ DFAR252.227-7013,  et seq.,  or its  successor.  Use  of the
+ microcode    by    the    U.S.     Government    constitutes
+ acknowledgement  of   AMD's  proprietary  rights   in  them.
+ ============================================================
+*/
+
+
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+
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+
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diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index 2e8bbfe09d..cf11135671 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -157,6 +157,7 @@ static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
 	{ X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
 	{ X86_VENDOR_AMD, 0x100F81 },           /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x100FA0 },           /* PH-E0 */
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/amd/model_10xxx/update_microcode.c b/src/cpu/amd/model_10xxx/update_microcode.c
index fa3b4f8a72..a9faafa470 100644
--- a/src/cpu/amd/model_10xxx/update_microcode.c
+++ b/src/cpu/amd/model_10xxx/update_microcode.c
@@ -51,6 +51,7 @@ static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
  * 00100F62h (DA-C2)     1062h                  0100009Fh
  * 00100F63h (DA-C3)     1043h                  010000b6h
  * 00100F81h (HY-D1)     1081h                  010000c4h
+ * 00100FA0h (PH-E0)     10A0h                  010000bfh
  */
 
 #include CONFIG_AMD_UCODE_PATCH_FILE
@@ -78,6 +79,7 @@ static u32 get_equivalent_processor_rev_id(u32 orig_id) {
 		0x100f62, 0x1062,
 		0x100f63, 0x1043,
 		0x100f81, 0x1081,
+		0x100fa0, 0x10A0,
 	};
 
 	u32 new_id;
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 78526681b9..d2bef3868e 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -46,6 +46,7 @@
 #define	AMD_RB_C3	0x08000000	/* ??? C3 */
 #define	AMD_DA_C3	0x10000000	/* XXXX C3 */
 #define	AMD_HY_D1	0x20000000	/* Istanbul D1 */
+#define	AMD_PH_E0	0x40000000	/* Phenom II X4 X6 */
 
 /*
  * Groups - Create as many as you wish, from the above public values
@@ -64,7 +65,7 @@
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_GT_Bx	(AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
-#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1)
+#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
 #define AMD_FAM10_LT_D  (AMD_FAM10_ALL & ~(AMD_HY_D0))
 #define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
 #define	AMD_DA_Cx       (AMD_DA_C2 | AMD_DA_C3)