diff options
| author | David Hendricks <dhendrix@chromium.org> | 2013-04-18 13:46:00 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-04-19 23:10:05 +0200 |
| commit | 8d5bc9f7726ac70e1c1a4f293827d67628650824 (patch) | |
| tree | 43e69817aab16a1aaa90b9a8af57bd0774e323fc /src | |
| parent | 95399327193f9ae23b6cd323cac6a0383c269865 (diff) | |
google/snow: disable unused USB3.0 PLL to save power
This PLL is unused and can be disabled to save about 250mW.
Change-Id: I1be37304d6ea5ff78696e05ad1023ce3c57f636c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/3109
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/snow/ramstage.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1cd84e841d..54d13d38f4 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -198,6 +198,16 @@ static struct video_info snow_dp_video_info = { #define EXYNOS5250_DP1_BASE 0x145b0000 #define SNOW_MAX_DP_TRIES 5 +/* + * This function disables the USB3.0 PLL to save power + */ +static void disable_usb30_pll(void) +{ + enum exynos5_gpio_pin usb3_pll_l = GPIO_Y11; + + gpio_direction_output(usb3_pll_l, 0); +} + /* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { @@ -215,6 +225,9 @@ static void mainboard_init(device_t dev) /* Clock Gating all the unused IP's to save power */ clock_gate(); + /* Disable USB3.0 PLL to save 250mW of power */ + disable_usb30_pll(); + snow_lcd_vdd(); do { udelay(50); |