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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-18 12:40:38 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-21 05:30:19 +0000 |
| commit | 8a6907c59219787d32608e1579b431a0ea2bffe4 (patch) | |
| tree | c1d29a33a5dd9061195a8d73cba007e879edcfa4 /src | |
| parent | e380a43803135f85ce5c0ebf8b836014a64259e6 (diff) | |
include/pci_def.h: Add some PCI Power Management CSR bits
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I84c8470764a4e6e09220044966111ffe72078099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55674
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/device/pci_def.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index d18e750520..22a5390e05 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -233,6 +233,10 @@ #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ +#define PCI_PM_CTRL_POWER_STATE_D0 0x0 +#define PCI_PM_CTRL_POWER_STATE_D1 0x1 +#define PCI_PM_CTRL_POWER_STATE_D2 0x2 +#define PCI_PM_CTRL_POWER_STATE_D3HOT 0x3 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |