soc/intel/skylake: Enable TraceHub depending on devicetree configuration

Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.

I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.

Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

17 files changed, 3 insertions, 17 deletions

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 377de0b951..06a435e17b 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -49,7 +49,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 14d8cc40c3..96e2217f89 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -42,7 +42,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 0ce9002d7d..a5bc167fdf 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -73,7 +73,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 856d749009..2160567043 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "1"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 4af8c42958..0f67de1d48 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index bed537bdb6..e53a7b565d 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index e9f8b1d8a5..172f402a3a 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -37,7 +37,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "SaImguEnable" = "0"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index de14503a88..94e2229daf 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 24ee14c3d1..0e2d7c9094 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -43,7 +43,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 3b9c76168f..28a852ff6a 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -48,7 +48,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "SaImguEnable" = "0"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index eb3cff351c..83e4638925 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -38,7 +38,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "1"
 	register "SaImguEnable" = "1"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index 08d80d5750..b158ed8ee2 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -50,7 +50,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "0"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index d1f0d4b205..a9380f86fc 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -39,7 +39,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "0"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index b9d385b8e3..96f4358570 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -55,7 +55,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 7e96fe269e..0fd25c58d1 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -35,7 +35,6 @@ chip soc/intel/skylake
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
-	register "EnableTraceHub" = "0"
 	register "SsicPortEnable" = "0"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "0"
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 243e6ee851..f670e0878f 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -175,7 +175,6 @@ struct soc_intel_skylake_config {
 	u8 IoBufferOwnership;
 
 	/* Trace Hub function */
-	u8 EnableTraceHub;
 	u32 TraceHubMemReg0Size;
 	u32 TraceHubMemReg1Size;
 
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 8e789bce80..76f7a7304c 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -293,7 +293,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	/* DCI and TraceHub configs */
 	m_t_cfg->PchDciEn = config->PchDciEn;
-	m_cfg->EnableTraceHub = config->EnableTraceHub;
+
+	dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
+	m_cfg->EnableTraceHub = dev ? dev->enabled : 0;
 	m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
 	m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;