soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO access

Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC
chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers
while only allowing GPIO accesses through the GPIO API on the SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

9 files changed, 49 insertions, 24 deletions

diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index bd963203e3..846dae9552 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/acpimmio_legacy_gpio100.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <southbridge/amd/common/amd_pci_util.h>
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index f29b846a80..313a71564f 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/acpimmio_legacy_gpio100.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c
index e01131d18e..c086709fcd 100644
--- a/src/mainboard/amd/thatcher/bootblock.c
+++ b/src/mainboard/amd/thatcher/bootblock.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/acpimmio_legacy_gpio100.h>
 #include <bootblock_common.h>
 #include <console/console.h>
 #include <superio/smsc/lpc47n217/lpc47n217.h>
diff --git a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c
index c5704c9193..3302556113 100644
--- a/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/variants/frontrunner-af/mainboard.c
@@ -2,6 +2,7 @@
 
 #include <stdlib.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/acpimmio_legacy_gpio100.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <southbridge/amd/common/amd_pci_util.h>
diff --git a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c
index 8992594525..09695d4b85 100644
--- a/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/variants/toucan-af/mainboard.c
@@ -2,6 +2,7 @@
 
 #include <stdlib.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/acpimmio_legacy_gpio100.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <southbridge/amd/common/amd_pci_util.h>
diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c
index f6b7a9a7dc..2c2eb9f7bd 100644
--- a/src/mainboard/pcengines/apu1/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu1/gpio_ftns.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <stdint.h>
-#include <amdblocks/acpimmio.h>
+#include <amdblocks/acpimmio_legacy_gpio100.h>
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 #include "gpio_ftns.h"
 
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 6f566341eb..f32558aa59 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -31,6 +31,16 @@ static inline void gpio_write32(gpio_t gpio_num, uint32_t value)
 	write32(gpio_ctrl_ptr(gpio_num), value);
 }
 
+static inline uint8_t iomux_read8(uint8_t reg)
+{
+	return read8(acpimmio_iomux + reg);
+}
+
+static inline void iomux_write8(uint8_t reg, uint8_t value)
+{
+	write8(acpimmio_iomux + reg, value);
+}
+
 static uint8_t get_gpio_mux(gpio_t gpio)
 {
 	return iomux_read8(gpio);
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index bf84a2564e..c9d709b9a3 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -272,18 +272,6 @@ static inline void smbus_write8(uint8_t reg, uint8_t value)
 	write8(acpimmio_smbus + reg, value);
 }
 
-/* These iomux_read/write8 are to be deprecated to enforce proper
-   use of <gpio.h> API for pin configurations. */
-static inline uint8_t iomux_read8(uint8_t reg)
-{
-	return read8(acpimmio_iomux + reg);
-}
-
-static inline void iomux_write8(uint8_t reg, uint8_t value)
-{
-	write8(acpimmio_iomux + reg, value);
-}
-
 static inline uint8_t misc_read8(uint8_t reg)
 {
 	return read8(acpimmio_misc + reg);
@@ -314,17 +302,6 @@ static inline void misc_write32(uint8_t reg, uint32_t value)
 	write32(acpimmio_misc + reg, value);
 }
 
-/* Old GPIO configuration registers */
-static inline uint8_t gpio_100_read8(uint8_t reg)
-{
-	return read8(acpimmio_gpio_100 + reg);
-}
-
-static inline void gpio_100_write8(uint8_t reg, uint8_t value)
-{
-	write8(acpimmio_gpio_100 + reg, value);
-}
-
 static inline uint8_t xhci_pm_read8(uint8_t reg)
 {
 	return read8(acpimmio_xhci_pm + reg);
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_legacy_gpio100.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_legacy_gpio100.h
new file mode 100644
index 0000000000..e7ef80a760
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_legacy_gpio100.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef AMD_BLOCK_ACPIMMIO_LEGACY_GPIO_100_H
+#define AMD_BLOCK_ACPIMMIO_LEGACY_GPIO_100_H
+
+#include <amdblocks/acpimmio.h>
+#include <device/mmio.h>
+#include <types.h>
+
+/* These iomux_read/write8 are to be deprecated to enforce proper
+   use of <gpio.h> API for pin configurations. */
+static inline uint8_t iomux_read8(uint8_t reg)
+{
+	return read8(acpimmio_iomux + reg);
+}
+
+static inline void iomux_write8(uint8_t reg, uint8_t value)
+{
+	write8(acpimmio_iomux + reg, value);
+}
+
+/* Old GPIO configuration registers */
+static inline uint8_t gpio_100_read8(uint8_t reg)
+{
+	return read8(acpimmio_gpio_100 + reg);
+}
+
+static inline void gpio_100_write8(uint8_t reg, uint8_t value)
+{
+	write8(acpimmio_gpio_100 + reg, value);
+}
+
+#endif /* AMD_BLOCK_ACPIMMIO_LEGACY_GPIO_100_H */