diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-12-05 02:45:51 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-09 21:53:58 +0000 |
| commit | 8474f4dc9bfd46bcb111cd3257006057b46d7f08 (patch) | |
| tree | b838a509b572a575c18a65c349d685dab01bcb86 /src | |
| parent | 83d54c30fae74a869288e38ad782c384b1621b6b (diff) | |
soc/intel/tigerlake: Drop unused SataEnable setting
`SataEnable` is set by some boards, but it doesn't have any effect since
its related FSP option is hooked up to the devicetree state. Thus, drop
it.
Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 9ed8fb299e..643bdc1bf7 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/tigerlake # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SataEnable" = "1" register "SataMode" = "0" register "SataSalpSupport" = "1" diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index eee29ef2ce..ca9661f09f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -146,7 +146,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA - register "SataEnable" = "1" register "SataMode" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index e729e8c0ee..09c8db1caf 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -215,7 +215,6 @@ struct soc_intel_tigerlake_config { uint8_t SlowSlewRate; /* SATA related */ - uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; |