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| author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-05-24 11:24:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-06 12:20:32 +0000 |
| commit | 82390fad4932f3bc6c2616684db4f2cbfc74b677 (patch) | |
| tree | 4077471ba4c93a5b6f2f2365084130faf6077cf3 /src | |
| parent | a47dc10ea59311aa161c7b900b171d0a101d2cdc (diff) | |
soc/intel/xeon_sp/spr: Add RMT config
This commit adds a configuration option to enable RMT in the coreboot
build for the Intel Xeon SP SPR platform.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 7 |
2 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 308ec2d45e..f666ab5dae 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -182,4 +182,10 @@ config ENABLE_IO_MARGINING ASPM. This option is intended for debugging and validation and should normally be disabled. +config ENABLE_RMT + bool "Enable RMT" + default n + help + Enable Rank Margining Tool. This option is intended for debugging and + validation and should normally be disabled. endif diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 8f4e98eea4..fef4d94d0f 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -217,6 +217,13 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.KtiLinkL1En = 0; mupd->FspmConfig.KtiLinkL0pEn = 0; } + + if (CONFIG(ENABLE_RMT)) { + printk(BIOS_INFO, "RMT Enabled.\n"); + mupd->FspmConfig.EnableRMT = 0x1; + /* Set FSP debug message to Max for RMT logs */ + mupd->FspmConfig.serialDebugMsgLvl = 0x3; + } } static uint8_t get_error_correction_type(const uint8_t RasModesEnabled) |