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authorNico Huber <nico.huber@secunet.com>2021-09-07 16:38:13 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-09-08 18:51:34 +0000
commit81638b546e8dfc85a437e8d2a5b72990a7ad87f7 (patch)
tree74c122655b707be905392218cd9876bcb4e50514 /src
parenteb7d91bf89f4691e859cbfdb036136361c9d05f6 (diff)
mb/lenovo/x220: Fix override trees
`chip` entries always need a device node below them to actually get hooked up. Change-Id: Ia5c573e582dab542b2a2a969c17581b0da6ed74e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57472 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/lenovo/x220/variants/x1/overridetree.cb1
-rw-r--r--src/mainboard/lenovo/x220/variants/x220/overridetree.cb1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
index 68a70f08ce..d2361396f2 100644
--- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
+++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
@@ -26,6 +26,7 @@ chip northbridge/intel/sandybridge
device pci 1c.3 off end # PCIe Port #4
device pci 1f.0 on #LPC bridge
chip ec/lenovo/h8
+ device pnp ff.2 on end # dummy
register "config2" = "0xe0"
register "config3" = "0xc0"
diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
index 604eadf2a9..8e939fd14c 100644
--- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
+++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
@@ -3,6 +3,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device pci 1f.0 on #LPC bridge
chip ec/lenovo/h8
+ device pnp ff.2 on end # dummy
register "eventa_enable" = "0x01"
register "eventb_enable" = "0xf0"
end