removed unused code, code reformat

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 111 insertions, 250 deletions

diff --git a/src/mainboard/ibm/e325/mainboard.c b/src/mainboard/ibm/e325/mainboard.c
index e7b4cf464f..01969d6448 100644
--- a/src/mainboard/ibm/e325/mainboard.c
+++ b/src/mainboard/ibm/e325/mainboard.c
@@ -31,6 +31,7 @@ static void enumerate(struct chip *chip)
 		printk_debug("Enumerating: %s\n", chip->control->name);
 	}
 
+	/* update device operation for dynamic root */
 	dev_root.ops = &mainboard_operations;
 	chip->dev = &dev_root;
 	chip->bus = 0;
diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index 84df9b1ab9..721badb52a 100644
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -6,26 +6,42 @@ uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
 uses MAINBOARD
 uses ARCH
+uses HAVE_HARD_RESET
 uses HARD_RESET_BUS
 uses HARD_RESET_DEVICE
 uses HARD_RESET_FUNCTION
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
 
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+default HARD_RESET_BUS=3
+default HARD_RESET_DEVICE=4
+default HARD_RESET_FUNCTION=0
 
-#
-#
 ###
-### Build the objects we have code for in this directory.
+### Build code to export a programmable irq routing table
 ###
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
 
-config chip.h
-register "fixup_scsi" = "1"
-register "fixup_vga" = "1"
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
 
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
 
 ##
 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
@@ -34,22 +50,43 @@ default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
 default LB_CKS_LOC=123
 
+###
+### Build code for SMP support
+### Only worry about 2 micro processors
+###
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+
+#
+###
+### Build code to setup a generic IOAPIC
+###
+default CONFIG_IOAPIC=1
+
+###
+### Clean up the motherboard id strings
+###
+default MAINBOARD_PART_NUMBER="S2885"
+default MAINBOARD_VENDOR="Tyan"
+
+###
+### Set all of the defaults for an x86 architecture
+###
+
+arch i386 end
+
+###
+### Build the objects we have code for in this directory.
+###
 driver mainboard.o
 #dir /drvers/adaptec/7902
 #dir /drivers/si/3114
 #dir /drivers/intel/82551
-driver ti_firewire.o
+#driver ti_firewire.o
 #dir /drivers/vga
 
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-default HARD_RESET_BUS=3
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-#
-#
-arch i386 end
 
 #
 ###
@@ -72,7 +109,7 @@ else
 	mainboardinit cpu/i386/reset32.inc 
 	ldscript /cpu/i386/reset32.lds 
 end
-#
+
 #### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
 #
@@ -149,6 +186,9 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
 ### Include the secondary Configuration files 
 ###
 dir /pc80
+config chip.h
+register "fixup_scsi" = "1"
+register "fixup_vga" = "1"
 
 northbridge amd/amdk8 "mc0"
         pci 0:18.0
@@ -192,7 +232,7 @@ northbridge amd/amdk8 "mc0"
                         pnp 2e.5 on #  Keyboard
                                  io 0x60 = 0x60
                                  io 0x62 = 0x64
-                               irq 0x70 = 1
+                                irq 0x70 = 1
 				irq 0x72 = 12
                         pnp 2e.6 off #  CIR
                         pnp 2e.7 off #  GAME_MIDI_GIPO1
@@ -218,11 +258,9 @@ northbridge amd/amdk8 "mc1"
         pci 0:19.3
 end
 
-#dir /bioscall
-
 cpu k8 "cpu0"
-  register "ldt0" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
-  register "ldt2" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
+	register "ldt0" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
+  	register "ldt2" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 end
 
 cpu k8 "cpu1"
diff --git a/src/mainboard/tyan/s2885/auto.c b/src/mainboard/tyan/s2885/auto.c
index 712ff731d1..e4c99d88ef 100644
--- a/src/mainboard/tyan/s2885/auto.c
+++ b/src/mainboard/tyan/s2885/auto.c
@@ -1,5 +1,4 @@
 #define ASSEMBLY 1
- 
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -26,38 +25,37 @@
 
 static void hard_reset(void)
 {
-        set_bios_reset();
+	set_bios_reset();
 
-        /* enable cf9 */
-        pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
+	/* enable cf9 */
+	pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+	/* reset */
+	outb(0x0e, 0x0cf9);
 }
 
 static void soft_reset(void)
 {
-        set_bios_reset();
-        pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+	set_bios_reset();
+	pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
 }
 
 static void memreset_setup(void)
 {
-   if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-   }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
+	if (is_cpu_pre_c0()) {
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
+	} else {
+		outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
+	}
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
-   if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
-   }
+	if (is_cpu_pre_c0()) {
+		udelay(800);
+		outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+		udelay(90);
+	}
 }
 
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -84,21 +82,21 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
 	 *     [3] Route to Link 2
 	 */
 
-	uint32_t ret=0x00010101; /* default row entry */
+	uint32_t ret = 0x00010101; /* default row entry */
 
+	/* CPU0 LDT1 <-> LDT1 CPU1 */
 	static const unsigned int rows_2p[2][2] = {
 		{ 0x00050101, 0x00010404 },
 		{ 0x00010404, 0x00050101 }
 	};
 
-	if(maxnodes>2) {
+	if (maxnodes > 2) {
 		print_debug("this mainboard is only designed for 2 cpus\r\n");
-		maxnodes=2;
+		maxnodes = 2;
 	}
 
-
-	if (!(node>=maxnodes || row>=maxnodes)) {
-		ret=rows_2p[node][row];
+	if (!(node >= maxnodes || row >= maxnodes)) {
+		ret = rows_2p[node][row];
 	}
 
 	return ret;
@@ -168,68 +166,43 @@ static void main(void)
         int needs_reset;
         enable_lapic();
         init_timer();
+
         if (cpu_init_detected()) {
-                asm("jmp __cpu_reset");
+                asm volatile ("jmp __cpu_reset");
         }
+
         distinguish_cpu_resets();
         if (!boot_cpu()) {
                 stop_this_cpu();
         }
+
         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
+
         setup_s2885_resource_map();
         needs_reset = setup_coherent_ht_domain();
-#if 0
-        needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
-#else
         needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
-#endif
         if (needs_reset) {
                 print_info("ht reset -\r\n");
                 soft_reset();
         }
-#if 0
-        dump_pci_devices();
-#endif
 
 #if 0
 	print_pci_devices();
 #endif
+
 	enable_smbus();
+
 #if 0
 	dump_spd_registers(&cpu[0]);
 #endif
+
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
 #if 0
 	dump_pci_devices();
-#endif
-#if 0
 	dump_pci_device(PCI_DEV(0, 0x18, 1));
 #endif
-
-	/* Check all of memory */
-#if 0
-	msr_t msr;
-	msr = rdmsr(TOP_MEM2);
-	print_debug("TOP_MEM2: ");
-	print_debug_hex32(msr.hi);
-	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
-#endif
-/*
-#if  0
-	ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#else 
-#if TOTAL_CPUS < 2
-	// Check 16MB of memory @ 0
-	ram_check(0x00000000, 0x00100000);
-#else
-	// Check 16MB of memory @ 2GB 
-	ram_check(0x80000000, 0x80100000);
-#endif
-#endif
-*/
 }
diff --git a/src/mainboard/tyan/s2885/failover.c b/src/mainboard/tyan/s2885/failover.c
index b22abfea06..95d675bc20 100644
--- a/src/mainboard/tyan/s2885/failover.c
+++ b/src/mainboard/tyan/s2885/failover.c
@@ -60,17 +60,17 @@ static void main(void)
 		goto fallback_image;
 	}
  normal_image:
-	asm("jmp __normal_image" 
-		: /* outputs */ 
-		: "a" (bist) /* inputs */
-		: /* clobbers */
-		);
+	asm volatile ("jmp __normal_image" 
+		      : /* outputs */ 
+		      : "a" (bist) /* inputs */
+		      : /* clobbers */
+		      );
  cpu_reset:
-	asm("jmp __cpu_reset"
-		: /* outputs */ 
-		: "a"(bist) /* inputs */
-		: /* clobbers */
-		);
+	asm volatile ("jmp __cpu_reset"
+		      : /* outputs */ 
+		      : "a"(bist) /* inputs */
+		      : /* clobbers */
+		      );
  fallback_image:
 #if HAVE_REGPARM_SUPPORT
 	return bist;
diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c
index 559f5b450e..2c01584310 100644
--- a/src/mainboard/tyan/s2885/mainboard.c
+++ b/src/mainboard/tyan/s2885/mainboard.c
@@ -9,164 +9,9 @@
 
 unsigned long initial_apicid[CONFIG_MAX_CPUS] =
 {
-	0,1
+	0, 1
 };
 
-#if 0
-static void fixup_lsi_53c1030(struct device *pdev)
-{
-//	uint8_t byte;
-	uint16_t word;
-
-	byte = 1;
-        pci_write_config8(pdev, 0xff, byte);
-           // Set the device id 
-//      pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030);
-           // Set the subsytem vendor id 
-//      pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);  
-        word = 0x10f1;
-	pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
-            // Set the subsytem id 
-	word = 0x2880;
-        pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
-            // Disable writes to the device id 
-	byte = 0;
-        pci_write_config8(pdev, 0xff, byte);
-
-//	lsi_scsi_init(pdev);
-	
-}
-#endif
-
-#if 0
-static void print_pci_regs(struct device *dev)
-{
-      uint8_t byte;
-      int i;
-
-      for(i=0;i<256;i++) {
-	     byte = pci_read_config8(dev, i);
-   
-             if((i%16)==0) printk_debug("\n%02x:",i);
-             printk_debug(" %02x",byte);
-      }
-      printk_debug("\n");
-	
-//        pci_write_config8(dev, 0x4, byte);
-
-}
-#endif
-#if 0
-static void print_mem(void)
-{
-        int i;
-	int low_1MB = 0;
-	for(i=low_1MB;i<low_1MB+1024*4;i++) {
-             if((i%16)==0) printk_debug("\n %08x:",i);
-             printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
-             }
-
-        for(i=low_1MB;i<low_1MB+1024*4;i++) {
-             if((i%16)==0) printk_debug("\n %08x:",i);
-             printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
-             }
- }
-#endif
-#if 0
-static void amd8111_enable_rom(void)
-{
-        uint8_t byte;
-        struct device *dev;
-
-        /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
-        /* Locate the amd8111 */
-        dev = dev_find_device(0x1022, 0x7468, 0);
-
-        /* Set the 4MB enable bit bit */
-        byte = pci_read_config8(dev, 0x43);
-        byte |= 0x80;
-        pci_write_config8(dev, 0x43, byte);
-}
-#endif
-#if 0
-static void onboard_scsi_fixup(void)
-{
-        struct device *dev;
-#if 1 
-	unsigned char i,j,k;
-
-	for(i=0;i<=6;i++) {
-		for(j=0;j<=0x1f;j++) {
-			for (k=0;k<=6;k++){
-				dev = dev_find_slot(i, PCI_DEVFN(j, k));
-				if (dev) {
-			                printk_debug("%02x:%02x:%02x",i,j,k);
-					print_pci_regs(dev);
-        			}
-			}
-		}
-	}
-#endif
-
-
-#if 0
-        dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
-        if(!dev) {
-                printk_info("LSI_SCSI_FW_FIXUP: No Device Found!");
-                return;
-        }
-
-	lsi_scsi_init(dev); 
-#endif
-//	print_mem();
-//	amd8111_enable_rom();
-}
-#endif
-#if 0
-static void vga_fixup(void) {
-        // we do this right here because:
-        // - all the hardware is working, and some VGA bioses seem to need
-        //   that
-        // - we need page 0 below for linuxbios tables.
-#if CONFIG_REALMODE_IDT == 1
-        printk_debug("INSTALL REAL-MODE IDT\n");
-        setup_realmode_idt();
-#endif
-#if CONFIG_VGABIOS == 1
-        printk_debug("DO THE VGA BIOS\n");
-        do_vgabios(0x0600);
-        post_code(0x93);
-#endif
-
-}
-
-#endif
- 
-
-static void
-enable(struct chip *chip, enum chip_pass pass)
-{
-
-        struct mainboard_tyan_s2885_config *conf = 
-		(struct mainboard_tyan_s2885_config *)chip->chip_info;
-
-        switch (pass) {
-		default: break;
-//		case CONF_PASS_PRE_CONSOLE:
-//		case CONF_PASS_PRE_PCI:
-//		case CONF_PASS_POST_PCI:		
-                case CONF_PASS_PRE_BOOT:
-//			if (conf->fixup_scsi)
- //       			onboard_scsi_fixup();
-//			if (conf->fixup_vga)
-//				vga_fixup();
-			printk_debug("mainboard fixup pass %d done\r\n",
-					pass);
-			break;
-	}
-
-}
-
 static struct device_operations mainboard_operations = {
         .read_resources   = root_dev_read_resources,
         .set_resources    = root_dev_set_resources,
@@ -180,6 +25,10 @@ static void enumerate(struct chip *chip)
 {
         struct chip *child;
 
+	if (chip->control && chip->control->name) {
+		printk_debug("Enumerating: %s\n", chip->control->name);
+	}
+
 	/* update device operation for dynamic root */
         dev_root.ops = &mainboard_operations;
         chip->dev = &dev_root;
@@ -188,8 +37,8 @@ static void enumerate(struct chip *chip)
 		child->bus = &dev_root.link[0];
         }
 }
+
 struct chip_control mainboard_tyan_s2885_control = {
-	.enable    = enable,
         .enumerate = enumerate,
         .name      = "Tyan s2885 mainboard ",
 };