diff options
| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2022-05-23 17:43:07 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-24 13:06:55 +0000 |
| commit | 79df32d083d7454ef73f7bd31b1c8e6237406385 (patch) | |
| tree | 47da09f40bc34253284f9192bd02585fc94ca3af /src | |
| parent | 236ad4c5c68ec1d254f86b53bc9d14fe1cdd357c (diff) | |
mb/google/brya/var/kinox: Update the DPTF parameters
Follow the Thermal_paramters_list-0520.xlsx to modify DPTF baseline PL1
values.
1. Modify baseline PL1 min_power from 15000 to 12000.
2. Modify baseline PL1 max_power from 17000 to 25000.
BUG=b:231380286
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ibd3098ee6bbf964cffddfcc9a4600cb7d81162d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/kinox/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index bb16785689..0ae60de544 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -144,8 +144,8 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 15000, - .max_power = 17000, + .min_power = 12000, + .max_power = 25000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC, .granularity = 500, |