diff options
| author | Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> | 2024-08-19 02:55:51 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-22 13:20:11 +0000 |
| commit | 752962e55390e47e02217eeb438ef20af6fa2166 (patch) | |
| tree | 7e118a9d69fc396a2e144996f66bcd8665165990 /src | |
| parent | 81b417da06cfbbfdae4d6eb817b46196f00d6207 (diff) | |
mb/lenovo/thinkcentre_m710s: Add SMBIOS data for PCIe slots
Change-Id: Iaa761108acbf275820ecbec9837b81bc5d64613e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83991
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb index f4f51b76ee..3eae80631d 100644 --- a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb @@ -5,6 +5,11 @@ chip soc/intel/skylake device domain 0 on device ref peg0 on # PCIE16X + smbios_slot_desc "SlotTypePciExpressGen3X16" + "SlotLengthLong" + "PCIE16X" + "SlotDataBusWidth16X" + # These configurations are technically for PCIe root # ports. However, they are used as there is no # equivalent for PEG devices. @@ -58,6 +63,11 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[4]" = "true" end device ref pcie_rp7 on # PCIE1X_2 + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "PCIE1X_2" + "SlotDataBusWidth1X" + register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "true" @@ -66,6 +76,11 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[6]" = "true" end device ref pcie_rp8 on # PCIE1X_1 + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "PCIE1X_1" + "SlotDataBusWidth1X" + register "PcieRpEnable[7]" = "true" register "PcieRpLtrEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "true" @@ -74,6 +89,11 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[7]" = "true" end device ref pcie_rp11 on # M2_WIFI + smbios_slot_desc "SlotTypeM2Socket1_SD" + "SlotLengthOther" + "M2_WIFI" + "SlotDataBusWidth1X" + register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "true" register "PcieRpClkReqSupport[10]" = "true" @@ -82,6 +102,11 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[10]" = "true" end device ref pcie_rp21 on # M2_SSD + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthOther" + "M2_SSD" + "SlotDataBusWidth1X" + register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "true" register "PcieRpClkReqSupport[20]" = "true" |