Add a generic register script handler

This is based on the RCBA configuration setup from haswell.
It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF.
I did not extend it to handle MSR yet but that would be another
potential register type.

There are a number of approaches to this kind of thing, but in the
end they have a lot of switch statements and a mass of #defines.
I'm not particularly set on any of the details so comments welcome.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=emerge-rambi chromeos-coreboot-rambi

Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175206
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4923
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

4 files changed, 743 insertions, 0 deletions

diff --git a/src/Kconfig b/src/Kconfig
index 4040705f20..531a8c860b 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1087,3 +1087,10 @@ config POWER_BUTTON_IS_OPTIONAL
 	default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
 	help
 	  Internal option that controls ENABLE_POWER_BUTTON visibility.
+
+config REG_SCRIPT
+	bool
+	default y if ARCH_X86
+	default n
+	help
+	  Internal option that controls whether we compile in register scripts.
diff --git a/src/include/reg_script.h b/src/include/reg_script.h
new file mode 100644
index 0000000000..18eda0c0d8
--- /dev/null
+++ b/src/include/reg_script.h
@@ -0,0 +1,316 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef REG_SCRIPT_H
+#define REG_SCRIPT_H
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/resource.h>
+
+/*
+ * The reg script library is a way to provide data-driven I/O accesses for
+ * initializing devices. It currently supports PCI, legacy I/O,
+ * memory-mapped I/O, and IOSF accesses.
+ *
+ * In order to simplify things for the developer the following features
+ * are employed:
+ * - Chaining of tables that allow runtime tables to chain to compile-time
+ *   tables.
+ * - Notion of current device (device_t) being worked on. This allows for
+ *   PCI config, io, and mmio on a particular device's resources.
+ *
+ * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
+ * and pop of the context. A chained reg_script inherits the previous
+ * context (such as current device), but it does not impact the previous
+ * context in any way.
+ */
+
+enum {
+	REG_SCRIPT_COMMAND_READ,
+	REG_SCRIPT_COMMAND_WRITE,
+	REG_SCRIPT_COMMAND_RMW,
+	REG_SCRIPT_COMMAND_POLL,
+	REG_SCRIPT_COMMAND_SET_DEV,
+	REG_SCRIPT_COMMAND_NEXT,
+	REG_SCRIPT_COMMAND_END,
+};
+
+enum {
+	REG_SCRIPT_TYPE_PCI,
+	REG_SCRIPT_TYPE_IO,
+	REG_SCRIPT_TYPE_MMIO,
+	REG_SCRIPT_TYPE_RES,
+	REG_SCRIPT_TYPE_IOSF,
+};
+
+enum {
+	REG_SCRIPT_SIZE_8,
+	REG_SCRIPT_SIZE_16,
+	REG_SCRIPT_SIZE_32,
+};
+
+struct reg_script {
+	uint32_t command;
+	uint32_t type;
+	uint32_t size;
+	uint32_t reg;
+	uint32_t mask;
+	uint32_t value;
+	uint32_t timeout;
+	union {
+		uint32_t id;
+		const struct reg_script *next;
+		device_t dev;
+		unsigned int res_index;
+	};
+};
+
+/* Internal helper Macros. */
+
+#define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
+			  mask_, value_, timeout_, id_)  \
+	{ .command = cmd_,     \
+	  .type = type_,       \
+	  .size = size_,       \
+	  .reg = reg_,         \
+	  .mask = mask_,       \
+	  .value = value_,     \
+	  .timeout = timeout_, \
+	  .id = id_,           \
+	}
+
+#define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
+			       mask_, value_, timeout_)  \
+	{ .command = cmd_,         \
+	  .type = type_,           \
+	  .size = size_,           \
+	  .reg = reg_,             \
+	  .mask = mask_,           \
+	  .value = value_,         \
+	  .timeout = timeout_,     \
+	  .res_index = res_index_, \
+	}
+
+/*
+ * PCI
+ */
+
+#define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
+	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,          \
+			       REG_SCRIPT_TYPE_PCI,                \
+			       REG_SCRIPT_SIZE_##bits_,            \
+			       reg_, mask_, value_, timeout_, 0)
+#define REG_PCI_READ8(reg_) \
+	REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
+#define REG_PCI_READ16(reg_) \
+	REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
+#define REG_PCI_READ32(reg_) \
+	REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
+#define REG_PCI_WRITE8(reg_, value_) \
+	REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
+#define REG_PCI_WRITE16(reg_, value_) \
+	REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
+#define REG_PCI_WRITE32(reg_, value_) \
+	REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
+#define REG_PCI_RMW8(reg_, mask_, value_) \
+	REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
+#define REG_PCI_RMW16(reg_, mask_, value_) \
+	REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
+#define REG_PCI_RMW32(reg_, mask_, value_) \
+	REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
+#define REG_PCI_OR8(reg_, value_) \
+	REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
+#define REG_PCI_OR16(reg_, value_) \
+	REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
+#define REG_PCI_OR32(reg_, value_) \
+	REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
+#define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
+#define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
+#define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
+
+/*
+ * Legacy IO
+ */
+
+#define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
+	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,         \
+			       REG_SCRIPT_TYPE_IO,                \
+			       REG_SCRIPT_SIZE_##bits_,           \
+			       reg_, mask_, value_, timeout_, 0)
+#define REG_IO_READ8(reg_) \
+	REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
+#define REG_IO_READ16(reg_) \
+	REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
+#define REG_IO_READ32(reg_) \
+	REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
+#define REG_IO_WRITE8(reg_, value_) \
+	REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
+#define REG_IO_WRITE16(reg_, value_) \
+	REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
+#define REG_IO_WRITE32(reg_, value_) \
+	REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
+#define REG_IO_RMW8(reg_, mask_, value_) \
+	REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
+#define REG_IO_RMW16(reg_, mask_, value_) \
+	REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
+#define REG_IO_RMW32(reg_, mask_, value_) \
+	REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
+#define REG_IO_OR8(reg_, value_) \
+	REG_SCRIPT_IO_RMW8(_reg, 0xff, value)
+#define REG_IO_OR16(reg_, value_) \
+	REG_SCRIPT_IO_RMW16(_reg, 0xffff, value)
+#define REG_IO_OR32(reg_, value_) \
+	REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value)
+#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
+#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
+#define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
+
+/*
+ * Memory Mapped IO
+ */
+
+#define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
+	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,           \
+			       REG_SCRIPT_TYPE_MMIO,                \
+			       REG_SCRIPT_SIZE_##bits_,             \
+			       reg_, mask_, value_, timeout_, 0)
+#define REG_MMIO_READ8(reg_) \
+	REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
+#define REG_MMIO_READ16(reg_) \
+	REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
+#define REG_MMIO_READ32(reg_) \
+	REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
+#define REG_MMIO_WRITE8(reg_, value_) \
+	REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
+#define REG_MMIO_WRITE16(reg_, value_) \
+	REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
+#define REG_MMIO_WRITE32(reg_, value_) \
+	REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
+#define REG_MMIO_RMW8(reg_, mask_, value_) \
+	REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
+#define REG_MMIO_RMW16(reg_, mask_, value_) \
+	REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
+#define REG_MMIO_RMW32(reg_, mask_, value_) \
+	REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
+#define REG_MMIO_OR8(reg_, value_) \
+	REG_MMIO_RMW8(reg_, 0xff, value_)
+#define REG_MMIO_OR16(reg_, value_) \
+	REG_MMIO_RMW16(reg_, 0xffff, value_)
+#define REG_MMIO_OR32(reg_, value_) \
+	REG_MMIO_RMW32(reg_, 0xffffffff, value_)
+#define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
+#define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
+#define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
+
+/*
+ * Access through a device's resource such as a Base Address Register (BAR)
+ */
+
+#define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
+	_REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_,                \
+			       REG_SCRIPT_TYPE_RES, bar_,                \
+			       REG_SCRIPT_SIZE_##bits_,                  \
+			       reg_, mask_, value_, timeout_)
+#define REG_RES_READ8(bar_, reg_) \
+	REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
+#define REG_RES_READ16(bar_, reg_) \
+	REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
+#define REG_RES_READ32(bar_, reg_) \
+	REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
+#define REG_RES_WRITE8(bar_, reg_, value_) \
+	REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
+#define REG_RES_WRITE16(bar_, reg_, value_) \
+	REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
+#define REG_RES_WRITE32(bar_, reg_, value_) \
+	REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
+#define REG_RES_RMW8(bar_, reg_, mask_, value_) \
+	REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
+#define REG_RES_RMW16(bar_, reg_, mask_, value_) \
+	REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
+#define REG_RES_RMW32(bar_, reg_, mask_, value_) \
+	REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
+#define REG_RES_OR8(bar_, reg_, value_) \
+	REG_RES_RMW8(bar_, reg_, 0xff, value_)
+#define REG_RES_OR16(bar_, reg_, value_) \
+	REG_RES_RMW16(bar_, reg_, 0xffff, value_)
+#define REG_RES_OR32(bar_, reg_, value_) \
+	REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
+#define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
+#define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
+#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
+
+/*
+ * IO Sideband Function
+ */
+
+#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
+	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,      \
+			       REG_SCRIPT_TYPE_IOSF,           \
+			       REG_SCRIPT_SIZE_32,             \
+			       reg_, mask_, value_, timeout_, unit_)
+#define REG_IOSF_READ(unit_, reg_) \
+	REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
+#define REG_IOSF_WRITE(unit_, reg_, value_) \
+	REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
+#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
+	REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
+#define REG_IOSF_OR(unit_, reg_, value_) \
+	REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
+#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
+	REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
+
+/*
+ * Chain to another table.
+ */
+#define REG_SCRIPT_NEXT(next_)                \
+	{ .command = REG_SCRIPT_COMMAND_NEXT, \
+	  .next = next_,                      \
+	}
+
+/*
+ * Set current device
+ */
+#define REG_SCRIPT_SET_DEV(dev_)                 \
+	{ .command = REG_SCRIPT_COMMAND_SET_DEV, \
+	  .dev = dev_,                           \
+	}
+
+/*
+ * Last script entry. All tables need to end with REG_SCRIPT_END.
+ */
+#define REG_SCRIPT_END \
+	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
+
+void reg_script_run(const struct reg_script *script);
+
+#endif /* REG_SCRIPT_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index f2b0fe3297..acd334e25d 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -110,6 +110,8 @@ ramstage-y += cbmem_info.c
 ramstage-y += hexdump.c
 romstage-y += hexdump.c
 
+ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c
+
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c
 
 ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
new file mode 100644
index 0000000000..252aa12651
--- /dev/null
+++ b/src/lib/reg_script.c
@@ -0,0 +1,418 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/resource.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <reg_script.h>
+
+#if CONFIG_SOC_INTEL_BAYTRAIL
+#include <baytrail/iosf.h>
+#endif
+
+#define POLL_DELAY 100 /* 100us */
+#if defined(__PRE_RAM__)
+#define EMPTY_DEV 0
+#else
+#define EMPTY_DEV NULL
+#endif
+
+struct reg_script_context {
+	device_t dev;
+	struct resource *res;
+	const struct reg_script *step;
+};
+
+static inline void reg_script_set_dev(struct reg_script_context *ctx,
+                                      device_t dev)
+{
+	ctx->dev = dev;
+	ctx->res = NULL;
+}
+
+static inline void reg_script_set_step(struct reg_script_context *ctx,
+                                       const struct reg_script *step)
+{
+	ctx->step = step;
+}
+
+static inline const struct reg_script *
+reg_script_get_step(struct reg_script_context *ctx)
+{
+	return ctx->step;
+}
+
+static struct resource *reg_script_get_resource(struct reg_script_context *ctx)
+{
+#if defined(__PRE_RAM__)
+	return NULL;
+#else
+	struct resource *res;
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	res = ctx->res;
+
+	if (res != NULL && res->index == step->res_index)
+		return res;
+
+	res = find_resource(ctx->dev, step->res_index);
+	ctx->res = res;
+	return res;
+#endif
+}
+
+static uint32_t reg_script_read_pci(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->size) {
+	case REG_SCRIPT_SIZE_8:
+		return pci_read_config8(ctx->dev, step->reg);
+	case REG_SCRIPT_SIZE_16:
+		return pci_read_config16(ctx->dev, step->reg);
+	case REG_SCRIPT_SIZE_32:
+		return pci_read_config32(ctx->dev, step->reg);
+	}
+	return 0;
+}
+
+static void reg_script_write_pci(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->size) {
+	case REG_SCRIPT_SIZE_8:
+		pci_write_config8(ctx->dev, step->reg, step->value);
+		break;
+	case REG_SCRIPT_SIZE_16:
+		pci_write_config16(ctx->dev, step->reg, step->value);
+		break;
+	case REG_SCRIPT_SIZE_32:
+		pci_write_config32(ctx->dev, step->reg, step->value);
+		break;
+	}
+}
+
+static uint32_t reg_script_read_io(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->size) {
+	case REG_SCRIPT_SIZE_8:
+		return inb(step->reg);
+	case REG_SCRIPT_SIZE_16:
+		return inw(step->reg);
+	case REG_SCRIPT_SIZE_32:
+		return inl(step->reg);
+	}
+	return 0;
+}
+
+static void reg_script_write_io(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->size) {
+	case REG_SCRIPT_SIZE_8:
+		outb(step->value, step->reg);
+		break;
+	case REG_SCRIPT_SIZE_16:
+		outw(step->value, step->reg);
+		break;
+	case REG_SCRIPT_SIZE_32:
+		outl(step->value, step->reg);
+		break;
+	}
+}
+
+static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->size) {
+	case REG_SCRIPT_SIZE_8:
+		return read8(step->reg);
+	case REG_SCRIPT_SIZE_16:
+		return read16(step->reg);
+	case REG_SCRIPT_SIZE_32:
+		return read32(step->reg);
+	}
+	return 0;
+}
+
+static void reg_script_write_mmio(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->size) {
+	case REG_SCRIPT_SIZE_8:
+		write8(step->reg, step->value);
+		break;
+	case REG_SCRIPT_SIZE_16:
+		write16(step->reg, step->value);
+		break;
+	case REG_SCRIPT_SIZE_32:
+		write32(step->reg, step->value);
+		break;
+	}
+}
+
+static uint32_t reg_script_read_res(struct reg_script_context *ctx)
+{
+	struct resource *res;
+	uint32_t val = 0;
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	res = reg_script_get_resource(ctx);
+
+	if (res == NULL)
+		return val;
+
+	if (res->flags & IORESOURCE_IO) {
+		const struct reg_script io_step = {
+			.size = step->size,
+			.reg = res->base + step->reg,
+		};
+		reg_script_set_step(ctx, &io_step);
+		val = reg_script_read_io(ctx);
+	}
+	else if (res->flags & IORESOURCE_MEM) {
+		const struct reg_script mmio_step = {
+			.size = step->size,
+			.reg = res->base + step->reg,
+		};
+		reg_script_set_step(ctx, &mmio_step);
+		val = reg_script_read_mmio(ctx);
+	}
+	reg_script_set_step(ctx, step);
+	return val;
+}
+
+static void reg_script_write_res(struct reg_script_context *ctx)
+{
+	struct resource *res;
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	res = reg_script_get_resource(ctx);
+
+	if (res == NULL)
+		return;
+
+	if (res->flags & IORESOURCE_IO) {
+		const struct reg_script io_step = {
+			.size = step->size,
+			.reg = res->base + step->reg,
+			.value = step->value,
+		};
+		reg_script_set_step(ctx, &io_step);
+		reg_script_write_io(ctx);
+	}
+	else if (res->flags & IORESOURCE_MEM) {
+		const struct reg_script mmio_step = {
+			.size = step->size,
+			.reg = res->base + step->reg,
+			.value = step->value,
+		};
+		reg_script_set_step(ctx, &mmio_step);
+		reg_script_write_mmio(ctx);
+	}
+	reg_script_set_step(ctx, step);
+}
+
+static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
+{
+#if CONFIG_SOC_INTEL_BAYTRAIL
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->id) {
+	case IOSF_PORT_BUNIT:
+		return iosf_bunit_read(step->reg);
+	case IOSF_PORT_DUNIT_CH0:
+		return iosf_dunit_ch0_read(step->reg);
+	case IOSF_PORT_PMC:
+		return iosf_punit_read(step->reg);
+	case IOSF_PORT_USBPHY:
+		return iosf_usbphy_read(step->reg);
+	case IOSF_PORT_USHPHY:
+		return iosf_ushphy_read(step->reg);
+	}
+#endif
+	return 0;
+}
+
+static void reg_script_write_iosf(struct reg_script_context *ctx)
+{
+#if CONFIG_SOC_INTEL_BAYTRAIL
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->id) {
+	case IOSF_PORT_BUNIT:
+		iosf_bunit_write(step->reg, step->value);
+		break;
+	case IOSF_PORT_DUNIT_CH0:
+		iosf_dunit_write(step->reg, step->value);
+		break;
+	case IOSF_PORT_PMC:
+		iosf_punit_write(step->reg, step->value);
+		break;
+	case IOSF_PORT_USBPHY:
+		iosf_usbphy_write(step->reg, step->value);
+		break;
+	case IOSF_PORT_USHPHY:
+		iosf_ushphy_write(step->reg, step->value);
+		break;
+	}
+#endif
+}
+
+static uint32_t reg_script_read(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->type) {
+	case REG_SCRIPT_TYPE_PCI:
+		return reg_script_read_pci(ctx);
+	case REG_SCRIPT_TYPE_IO:
+		return reg_script_read_io(ctx);
+	case REG_SCRIPT_TYPE_MMIO:
+		return reg_script_read_mmio(ctx);
+	case REG_SCRIPT_TYPE_RES:
+		return reg_script_read_res(ctx);
+	case REG_SCRIPT_TYPE_IOSF:
+		return reg_script_read_iosf(ctx);
+	}
+	return 0;
+}
+
+static void reg_script_write(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = reg_script_get_step(ctx);
+
+	switch (step->type) {
+	case REG_SCRIPT_TYPE_PCI:
+		reg_script_write_pci(ctx);
+		break;
+	case REG_SCRIPT_TYPE_IO:
+		reg_script_write_io(ctx);
+		break;
+	case REG_SCRIPT_TYPE_MMIO:
+		reg_script_write_mmio(ctx);
+		break;
+	case REG_SCRIPT_TYPE_RES:
+		reg_script_write_res(ctx);
+		break;
+	case REG_SCRIPT_TYPE_IOSF:
+		reg_script_write_iosf(ctx);
+		break;
+	}
+}
+
+static void reg_script_rmw(struct reg_script_context *ctx)
+{
+	uint32_t value;
+	const struct reg_script *step = reg_script_get_step(ctx);
+	struct reg_script write_step = *step;
+
+	value = reg_script_read(ctx);
+	value &= step->mask;
+	value |= step->value;
+	write_step.value = value;
+	reg_script_set_step(ctx, &write_step);
+	reg_script_write(ctx);
+	reg_script_set_step(ctx, step);
+}
+
+/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT
+ * as recursive call with a new context that has the same dev and resource
+ * as the previous one. That will run to completion and then move on to the
+ * next step of the previous context. */
+static void reg_script_run_next(struct reg_script_context *ctx,
+                                const struct reg_script *step);
+
+static void reg_script_run_with_context(struct reg_script_context *ctx)
+{
+	uint32_t value = 0, try;
+
+	while (1) {
+		const struct reg_script *step = reg_script_get_step(ctx);
+
+		if (step->command == REG_SCRIPT_COMMAND_END)
+			break;
+
+		switch (step->command) {
+		case REG_SCRIPT_COMMAND_READ:
+			(void)reg_script_read(ctx);
+			break;
+		case REG_SCRIPT_COMMAND_WRITE:
+			reg_script_write(ctx);
+			break;
+		case REG_SCRIPT_COMMAND_RMW:
+			reg_script_rmw(ctx);
+			break;
+		case REG_SCRIPT_COMMAND_POLL:
+			for (try = 0; try < step->timeout; try += POLL_DELAY) {
+				value = reg_script_read(ctx) & step->mask;
+				if (value == step->value)
+					break;
+				udelay(POLL_DELAY);
+			}
+			if (try >= step->timeout)
+				printk(BIOS_WARNING, "%s: POLL timeout waiting "
+				       "for 0x%08x to be 0x%08x, got 0x%08x\n",
+				       __func__, step->reg, step->value, value);
+			break;
+		case REG_SCRIPT_COMMAND_SET_DEV:
+			reg_script_set_dev(ctx, step->dev);
+			break;
+		case REG_SCRIPT_COMMAND_NEXT:
+			reg_script_run_next(ctx, step->next);
+			break;
+		default:
+			printk(BIOS_WARNING, "Invalid command: %08x\n",
+			       step->command);
+			break;
+		}
+
+		reg_script_set_step(ctx, step + 1);
+	}
+}
+
+static void reg_script_run_next(struct reg_script_context *prev_ctx,
+                                const struct reg_script *step)
+{
+	struct reg_script_context ctx;
+
+	/* Use prev context as a basis but start at a new step. */
+	ctx = *prev_ctx;
+	reg_script_set_step(&ctx, step);
+	reg_script_run_with_context(&ctx);
+}
+
+void reg_script_run(const struct reg_script *step)
+{
+	struct reg_script_context ctx;
+
+	reg_script_set_dev(&ctx, EMPTY_DEV);
+	reg_script_set_step(&ctx, step);
+	reg_script_run_with_context(&ctx);
+}