diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-12-14 16:57:37 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-12-16 01:38:35 +0100 |
| commit | 710032be191687adc5865e3ec5319e3b24940e03 (patch) | |
| tree | 392c234b74c3ed878235ff34d593cad2cebeadfa /src | |
| parent | a12fc81fef6a68b05fa9cddada3023bd84129532 (diff) | |
google/eve: Enable native mode for UART pins in bootblock
Put the UART pins into native mode in bootblock so they are not
floating when we try to communicate with H1 over I2C. Without
a serial console enabled BIOS these pins were not configured
until ramstage.
BUG=chrome-os-partner:60935
TEST=Boot Eve board without serial console and H1 TPM enabled
Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/eve/gpio.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h index c7a5e46793..34ae3a45b6 100644 --- a/src/mainboard/google/eve/gpio.h +++ b/src/mainboard/google/eve/gpio.h @@ -225,6 +225,10 @@ static const struct pad_config early_gpio_table[] = { /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */ /* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */ + +/* Ensure UART pins are in native mode for H1 */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ }; #endif |