diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-08 15:06:56 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2024-04-16 01:46:05 +0000 |
| commit | 6ef23316c235d14213d0bdc48c6853d3059a0b64 (patch) | |
| tree | 75e69d6b500ef33f32eaff750eb24c6f0496782e /src | |
| parent | fd46b497ead843eccfd80124ca8fbba7e57a3631 (diff) | |
sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask
Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of
the PCIe root port register at offset 0xf5.
Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index fd41ce8936..30a34f757a 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -662,7 +662,7 @@ static void pch_pcie_early(struct device *dev) /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25); - pci_and_config8(dev, 0xf5, 0x3f); + pci_and_config8(dev, 0xf5, 0x0f); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) pci_and_config8(dev, 0xf7, ~0x0c); |