soc/intel/xeon_sp/util: Enhance lock_pam0123

- Only compile code in ramstage
- Lock PAM on all sockets
- Instead of manually crafting S:B:D:F numbers for each PCI device
  search for the devices by PCI vendor and device ID.

This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.

Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

4 files changed, 18 insertions, 13 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 614f42af08..762e2e2fd8 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -13,6 +13,7 @@
 #define SAD_ALL_PAM0123_CSR		0x40
 #define   PAM_LOCK			BIT(0)
 #define SAD_ALL_PAM456_CSR		0x44
+#define SAD_ALL_DEVID			0x344f
 
 #if !defined(__SIMPLE_DEVICE__)
 #define _PCU_DEV(bus, func)		pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func))
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 8b3c36c7b7..ec5215321e 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -24,6 +24,7 @@
 #define SAD_ALL_PAM0123_CSR		0x40
 #define   PAM_LOCK			BIT(0)
 #define SAD_ALL_PAM456_CSR		0x44
+#define SAD_ALL_DEVID			0x2054
 
 #if !defined(__SIMPLE_DEVICE__)
 #define _PCU_DEV(bus, func)		pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func))
diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
index 1d7dedd82e..0ad5ea0870 100644
--- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h
@@ -35,6 +35,7 @@
 #define SAD_ALL_FUNC 0
 #define SAD_ALL_PAM0123_CSR 0x80
 #define SAD_ALL_PAM456_CSR 0x84
+#define SAD_ALL_DEVID 0x344f
 
 #if !defined(__SIMPLE_DEVICE__)
 #define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func))
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index 7fc903ab78..956973e8ea 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -17,19 +17,6 @@
 #include <soc/util.h>
 #include <timer.h>
 
-void lock_pam0123(void)
-{
-	if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT)
-		return;
-
-	/* section 16.3.19 of Intel doc. #612246 */
-	uint32_t pam0123_lock = 0x33333331;
-	uint32_t bus1 = get_socket_ubox_busno(0);
-
-	pci_s_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
-		SAD_ALL_PAM0123_CSR, pam0123_lock);
-}
-
 void unlock_pam_regions(void)
 {
 	uint32_t pam0123_unlock_dram = 0x33333330;
@@ -121,6 +108,21 @@ unsigned int soc_get_num_cpus(void)
 }
 
 #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */
+
+void lock_pam0123(void)
+{
+	const uint32_t pam0123_lock = 0x33333331;
+	struct device *dev;
+
+	if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT)
+		return;
+
+	dev = NULL;
+	/* Look for SAD_ALL devices on all sockets */
+	while ((dev = dev_find_device(PCI_VID_INTEL, SAD_ALL_DEVID, dev)))
+		pci_write_config32(dev, SAD_ALL_PAM0123_CSR, pam0123_lock);
+}
+
 /* return true if command timed out else false */
 static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask,
 				  uint32_t target)