diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-07-19 11:09:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-07-22 17:30:51 +0000 |
| commit | 6ad1357dad5109bb9e71a72c6ab53d18ea53b4cb (patch) | |
| tree | 5914bc2bde7de51999ab9fc64410e3662a0fc626 /src | |
| parent | 46caf3e37d6caefb40f1f86367b6bb929f368ff3 (diff) | |
mb/google/brya/var/trulo: Add PnP descriptions
This patch adds power related entries (FIVR and policy to control
lower power c-state transitioning) to the device tree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/trulo/overridetree.cb | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index d5cb4f624c..19a533d6b2 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -103,6 +103,21 @@ chip soc/intel/alderlake register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -123,6 +138,10 @@ chip soc/intel/alderlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # FIXME: To be enabled in future based on PNP impact data. + # Disable Package C-state demotion for nissa baseboard. + register "disable_package_c_state_demotion" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |