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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2022-09-06 17:26:18 +0530
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-09-20 08:03:55 +0000
commit69b00c6f1bd30ab3233d701d133cc600b5cec878 (patch)
treef40968604e67894c6b4bd04f44be0f042c723539 /src
parent25f6db4d2d91028a133712045db096b05589f3d6 (diff)
mb/google/brya/variants/skolas: Set power limit values
Skolas board is based on Raptor Lake SoC, not Alder Lake. The code change sets CPU power limit values as performance configuration based on various Raptor Lake SoC SKUs as per the document #686872. BUG=b:242869605 BRANCH=None TEST=Built and tested on skolas board Change-Id: Ieb3ca4ff77039412ef56da49e1b438f5e0b9db02 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/skolas/ramstage.c10
-rw-r--r--src/mainboard/google/brya/variants/skolas4es/ramstage.c10
2 files changed, 8 insertions, 12 deletions
diff --git a/src/mainboard/google/brya/variants/skolas/ramstage.c b/src/mainboard/google/brya/variants/skolas/ramstage.c
index 970c628f50..b468320356 100644
--- a/src/mainboard/google/brya/variants/skolas/ramstage.c
+++ b/src/mainboard/google/brya/variants/skolas/ramstage.c
@@ -5,12 +5,10 @@
const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
- /* All values are for baseline config as per bug:191906315 comment #10 */
- { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
- { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
- { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
- { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
- { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
+ /* All values are for performance config as per document #686872 */
+ { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
+ { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 },
+ { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 },
};
void variant_devtree_update(void)
diff --git a/src/mainboard/google/brya/variants/skolas4es/ramstage.c b/src/mainboard/google/brya/variants/skolas4es/ramstage.c
index 970c628f50..b468320356 100644
--- a/src/mainboard/google/brya/variants/skolas4es/ramstage.c
+++ b/src/mainboard/google/brya/variants/skolas4es/ramstage.c
@@ -5,12 +5,10 @@
const struct cpu_power_limits limits[] = {
/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
- /* All values are for baseline config as per bug:191906315 comment #10 */
- { PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000, 39000, 39000, 100000 },
- { PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000, 39000, 39000, 100000 },
- { PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000, 43000, 43000, 105000 },
- { PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000, 43000, 43000, 105000 },
- { PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 80000, 80000, 159000 },
+ /* All values are for performance config as per document #686872 */
+ { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 },
+ { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 },
+ { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 },
};
void variant_devtree_update(void)