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authorBora Guvendik <bora.guvendik@intel.com>2022-05-25 17:39:34 -0700
committerFelix Held <felix-coreboot@felixheld.de>2022-06-07 12:49:41 +0000
commit644502311571cf315fd2cdeb080a14f87d0b9e7c (patch)
tree5a21511f9b128d79aa63294668987d9e82538ea7 /src
parent6fbdedd1d240ab6958017c3dd28f1d3cfc99efc5 (diff)
mb/intel/adlrvp: Add VBT for adlrvp with Raptor Lake silicon
Board id is same so use cpuid to decide to use ADL or RPL VBT. BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=build adlrvp_rpl_ext_ec Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/adlrvp/mainboard.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index 8882671bfa..9862820a34 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -1,7 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/cpu.h>
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
+#include <cpu/intel/cpu_ids.h>
#include <device/device.h>
#include <drivers/intel/gma/opregion.h>
#include <ec/ec.h>
@@ -71,10 +73,13 @@ const char *mainboard_vbt_filename(void)
if (!CONFIG(CHROMEOS))
return "vbt.bin";
+ uint32_t cpu_id = cpu_get_cpuid();
uint8_t sku_id = get_board_id();
switch (sku_id) {
case ADL_P_LP5_1:
case ADL_P_LP5_2:
+ if (cpu_id == CPUID_RAPTORLAKE_P_J0)
+ return "vbt_adlrvp_rpl_lp5.bin";
return "vbt_adlrvp_lp5.bin";
case ADL_M_LP5:
return "vbt_adlrvp_m_lp5.bin";