diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-12-11 16:55:04 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-12-14 10:25:02 +0000 |
| commit | 63a078e66d3ecb9a8e23c914b5ee6d9e89ef4cf3 (patch) | |
| tree | a925c04ac29a05aa87a0c83e3bf792c0d1f2ed27 /src | |
| parent | 056c3a9ff25eab7daf57819ea2509a09cac52b62 (diff) | |
soc/intel/skylake: Drop unreferenced PttSwitch dt setting
The value for this setting is not used anywhere. Drop it.
Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
14 files changed, 0 insertions, 15 deletions
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 49e2964f45..0e408f808e 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -47,7 +47,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 6c1144b736..f8a92d88de 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -43,7 +43,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 22935f4520..430334af5f 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -74,7 +74,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index ba3f204d09..4f8beefd65 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -42,7 +42,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 2f230faf3f..4fd71d5cf6 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -49,7 +49,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index ed846f61e2..93836421f0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 5117c545f1..65ecc8f3f1 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -38,7 +38,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b1340f8058..ec55645a84 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2d077c29fc..6b58e0b048 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -44,7 +44,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 2a916fc1df..841823116c 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -49,7 +49,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index a3ee45c809..8e5caf3fb2 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index b796fbbc9c..6d98772af7 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -53,7 +53,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 15ea78538e..8f3e0d6bc3 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -33,7 +33,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 7b9871c21c..4184233484 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -299,8 +299,6 @@ struct soc_intel_skylake_config { u8 ScsEmmcHs400RxStrobeDll1; u8 ScsEmmcHs400TxDataDll; - u8 PttSwitch; - enum { Display_iGFX, Display_PEG, |