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authorFelix Held <felix-coreboot@felixheld.de>2021-11-09 00:55:38 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-11-10 00:13:56 +0000
commit5c163bb86926d982af1ffd93b072ca85070ca1e1 (patch)
tree0bca2c9e09233b18f22305dd9cab2ad9496eb923 /src
parente6a1ebe55ba6bbcd791e40a934bd3e65fad31cb9 (diff)
soc/amd/cezanne,picasso/include/southbridge: use bitwise or in defines
Use bitwise or instead of additions to build bit masks with multiple bits set. TEST=Timeless build results in identical image on amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h6
-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h6
2 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 1e3697bd59..b492088005 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -99,15 +99,15 @@
#define MISC_I2C1_PAD_CTRL 0xdc
#define MISC_I2C2_PAD_CTRL 0xe0
#define MISC_I2C3_PAD_CTRL 0xe4
-#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3))
+#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
#define I2C_PAD_CTRL_NG_NORMAL 0xc
-#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5))
+#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5))
#define I2C_PAD_CTRL_RX_SHIFT 4
#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6)
-#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8))
+#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8))
#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7
#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 300f458fa7..2936600abf 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -96,15 +96,15 @@
#define MISC_I2C1_PAD_CTRL 0xdc
#define MISC_I2C2_PAD_CTRL 0xe0
#define MISC_I2C3_PAD_CTRL 0xe4
-#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3))
+#define I2C_PAD_CTRL_NG_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
#define I2C_PAD_CTRL_NG_NORMAL 0xc
-#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5))
+#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) | BIT(5))
#define I2C_PAD_CTRL_RX_SHIFT 4
#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT)
#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6)
-#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8))
+#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) | BIT(8))
#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7
#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)