diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2019-02-28 23:55:30 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-04 14:00:34 +0000 |
| commit | 59e5c80237f76dfb5dff9b751aa23f30ef54a3af (patch) | |
| tree | 5d61519641df1930b987463efe39ef86556b48ff /src | |
| parent | 80505a6fef22587b5e5a4037d4e83c81236814fd (diff) | |
soc/intel/cannonlake: Fix DSDT compile remarks
The following remarks show up during cannonlake based platform coreboot
build:
dsdt.asl 55: Offset (0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 136: Offset (0xa8),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Address those two remarks in coreboot.
BUG=N/A
TEST=Build coreboot and check build log to see no more remark.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe
Reviewed-on: https://review.coreboot.org/c/31666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/globalnvs.asl | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/northbridge.asl | 8 |
2 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl index ac60b36d51..940cf4396b 100644 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ b/src/soc/intel/cannonlake/acpi/globalnvs.asl @@ -32,7 +32,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PCNT, 8, // 0x03 - Processor Count diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl index 68ab059422..7fb4c09179 100644 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ b/src/soc/intel/cannonlake/acpi/northbridge.asl @@ -54,11 +54,9 @@ Device (MCHC) , 11, DIBR, 20, /* DMIBAR [31:12] */ - Offset (0xa0), /* Top of Used Memory */ - TOM, 64, - - Offset (0xa8), /* Top of Upper Used Memory */ - TUUD, 64, + Offset (0xa0), + TOM, 64, /* Top of Used Memory */ + TUUD, 64, /* Top of Upper Used Memory */ Offset (0xbc), /* Top of Low Used Memory */ TLUD, 32, |